Publications
2018
 P. Fišer and V. Šimek, "Optimum Polymorphic Circuits Synthesis Method", in Proc. of 13th IEEE International Conference on Design and Technology of Integrated Systems in nanoscale era (DTIS), Taormina, Italy, April 1012, 2018, p. 6. pdf
 I. Háleček, P. Fišer, and J. Schmidt, "Towards AND/XOR Balanced Synthesis: Logic Circuits Rewriting with XOR," Microelectronics Reliability, Elsevier, ISSN: 00262714, vol. 81, February 2018, pp. 274286. doi
 J. Schmidt, and P. Fišer, "A Prudent Approach to Collection of Examples for Logic Synthesis and Optimization", in Further Improvements in the Boolean Domain (book chapter), Cambridge Scholars Publishing, Jan. 2018, ISBN 9781527503717, pp. 280301.
2017
 P. Fišer, I. Háleček, and J. Schmidt, "SATBased Generation of Optimum Function Implementations with XOR Gates", in Proc. of 20th Euromicro Conference on Digital Systems Design (DSD), Vienna, Austria, August 31September 1, 2017, pp. 163170. pdf
 R. Hülle, P. Fišer, and J. Schmidt, "SATbased ATPG for ZeroAliasing Compaction", in Proc. of 20th Euromicro Conference on Digital Systems Design (DSD), Vienna, Austria, August 31September 1, 2017, pp. 307314. pdf
 J. Bělohoubek, P. Fišer, and J. Schmidt, "Error Masking Method Based On The ShortDuration Offline Test," Microprocessors and Microsystems (MICPRO), Elsevier, vol. 52, July 2017, pp. 236250. doi
 I. Háleček, P. Fišer, J. Schmidt, "On XAIG Rewriting," in Proc. of 26th International Workshop on Logic & Synthesis (IWLS), Austin, TX, June 17 – 18, 2017, pp. 8996. pdf
 I. Háleček, P. Fišer, J. Schmidt, "Are XORs in logic synthesis really necessary?," in Proc. of IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Dresden (DE), April 1921, 2017, pp. 138143. pdf
2016
 R. Hülle, P. Fišer, J. Schmidt, and J. Borecký, "SATATPG for ApplicationOriented FPGA Testing", in Proc. of the 15th Biennial Baltic Electronics Conference (BEC), October 35, 2016, Tallinn, Estonia, pp. 8386. pdf
 J. Schmidt and P. Fišer, "A Prudent Approach to Benchmark Collection," in Proc. of 12th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 2223, 2016, pp. 129136. pdf
 P. Fišer and J. Schmidt, "A Comprehensive Set of Logic Synthesis and Optimization Examples," in Proc. of 12th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 2223, 2016, pp. 151158. pdf
 J. Bělohoubek, P. Fišer, and J. Schmidt, "Error Correction Method Based on the ShortDuration Offline Test," in Proc. of 19th Euromicro Conference on Digital Systems Design (DSD), Limassol, Cyprus, August 31September 2, 2016, pp. 495502. pdf
 J. Schmidt, R. B. Blažek, and P. Fišer, "Towards Understanding the Performance of Randomized Algorithms", in Problems and New Solutions in the Boolean Domain (book chapter), Cambridge Scholars Publishing, May 2016, pp. 167186.
 R. Tamáši, M. Siebert, P. Fišer, and E. Gramatová, "A New Method for Path Criticality Calculation," in Proc. of IEEE 19th International Symposium on Design and Diagnostics of
Electronic Circuits & Systems (DDECS), Košice (SK), April 2022, 2016, pp. 190193. pdf
 M. Lipovský, J. Švarc, E. Gramatová, and P. Fišer, "A New UserFriendly ATPG Platform for Digital Circuits," in Proc. of IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice (SK), April 2022, 2016, pp. 210213. pdf
 S. Das, P. Dasgupta, P. Fišer, S. Ghosh, D. K. Das, "A RuleBased Approach for Minimizing Power Dissipation of Digital Circuits," in Proc. of IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice (SK), April 2022, 2016, pp. 237242. pdf
2015
 I. Háleček, P. Fišer, and J. Schmidt, "On Identification of XOR Gates in AIGs," in Proc. of the Work in Progress Session of the 18th Euromicro Conference on Digital Systems Design (DSD), Fuchal, Madeira, Portugal, August 2628, 2015, 2 p. pdf
 J. Bělohoubek, P. Fišer, and J. Schmidt, "Novel CElement Based Error Detection and Correction Method Combining Time and Area Redundancy," in Proc. of 18th Euromicro Conference on Digital Systems Design (DSD), Fuchal, Madeira, Portugal, August 2628, 2015, pp. 280283. pdf
 R. Tamaši, M. Siebert, and P. Fišer, "A New Method for Specification of Parameters to Path Delay Faults Testing," in Proc. of the 3rd Prague Embedded Systems Workshop (PESW), July 24, 2015, Roztoky u Prahy (Czech Rep.), pp. 2632. pdf
 P. Fišer and J. Schmidt, "Introduction to Lethal Circuit Transformations," in Proc. of Design and Analysis of Control Systems, March 2023, 2015, Athens, Greece, p. 4. pdf
2014
 P. Fišer and J. Schmidt, "The Logic Synthesis Homework Is Not Done Yet", invited talk at 10th Italian Annual Seminar Day on Logic Synthesis. slides
 J. Balcárek, P. Fišer, and J. Schmidt, "On Don’t Cares in Test Compression", Microprocessors and Microsystems (MICPRO), Elsevier, Volume 38, Issue 8, Part A, November 2014, pp. 754–765. pdf, doi
 J. Schmidt, R. Blažek, and P. Fišer, "On Probability Density Distribution of Randomized Algorithms Performance," in Proc. of 11th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 1719, 2014, pp. 6774. pdf
 P. Fišer, J. Schmidt, and J. Balcárek, "On Robustness of EDA Tools," in Proc. of 17th Euromicro Conference on Digital Systems Design (DSD), Verona (Italy), August 2729, 2014, pp. 427434. pdf
 J. Balcárek, P. Fišer, and J. Schmidt, "PBOBased Test Compression," in Proc. of 17th Euromicro Conference on Digital Systems Design (DSD), Verona (Italy), August 2729, 2014, pp. 679682. pdf
 I. Lemberski, P. Fišer, and R. Suleimanov, "Asynchronous sumofproducts logic minimization and orthogonalization," in International Journal of Circuit Theory and Applications, John Wiley & Sons, Ltd., Vol. 42, Issue 6, June 2014, pp. 562–571. doi
 P. Fišer and J. Schmidt, "Permuting Variables to Improve Iterative Resynthesis," in Recent Progress in the Boolean Domain, Cambridge Scholars Publishing (book chapter), April 2014, pp. 213230.
 A. Bernasconi, V. Ciriani, P. Fišer, and G. Trucco, "Weighted Don't Cares in Logic Synthesis," in Recent Progress in the Boolean Domain (book chapter), Cambridge Scholars Publishing, April 2014, pp. 263277.
 P. Fišer, J. Schmidt, and J. Balcárek, "Sources of Bias in EDA Tools and Its Influence," in Proc. of 17th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Warsaw (Poland), April 2325, 2014, pp. 258261. pdf
 I. Lemberski and P. Fišer, "DualRail Asynchronous Logic MultiLevel Implementation," in Integration, the VLSI Journal, Elsevier, vol. 47, Issue 1, January 2014, pp. 148–159. pdf, doi
2013
 J. Schmidt, P. Fišer, J. Balcárek, "The influence of implementation type on dependability parameters", Microprocessors and Microsystems (MICPRO), Vol. 37, Issue 67, AugustOctober 2013, Elsevier, pp. 641648. pdf, doi
 Jan Pospíšil, Jan Schmidt, Petr Fišer, "New SEU Modeling by Architecture Analysis," in Proc. Work in Progress Session of 16th Euromicro Conference on Digital Systems Design (DSD), Santander (Spain), September 46, 2013.
 J. Balcárek, P. Fišer, and J. Schmidt, "Simulation and SAT Based ATPG for Compressed Test Generation," in Proc. of 16th Euromicro Conference on Digital Systems Design (DSD), Santander (Spain), September 46, 2013, pp. 445452. pdf
 J. Balcárek, P. Fišer, and J. Schmidt, "Techniques for SATbased Constrained Test Pattern Generation," in Microprocessors and Microsystems (MICPRO), Vol. 37, Issue 2, March 2013, Elsevier, pp. 185195. pdf, doi
2012
 P. Fišer, "Randomized Iterative Logic Synthesis Algorithms," Habilitation Thesis, Brno, 2012, p. 84.
 J. Schmidt, P. Fišer and J. Balcárek, "Generalized Miter and its Application in Hardware Design," in Proc. of the 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS), Znojmo (ČR), October 2528, 2012, pp. 119120.
 P. Fišer and J. Schmidt, "On Using Permutation of Variables to Improve the Iterative Power of Resynthesis," in Proc. of 10th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 1921, 2012, pp. 107114. pdf
 P. Fišer and J. Schmidt, "A Difficult Example Or a Badly Represented One?," in Proc. of 10th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 1921, 2012, pp. 115122. pdf
 A. Bernasconi, V. Ciriani, P. Fišer, and G. Trucco, "Weighted Don't Cares," in Proc. of 10th Int. Workshop on Boolean Problems (IWSBP), Freiberg, (Germany), September 1921, 2012, pp. 123130. pdf
 J. Schmidt, P. Fišer and J. Balcárek, "The Influence of Implementation Technology on Dependability Parameters," in Proc. of 15th Euromicro Conference on Digital Systems Design (DSD), Cesme (Turkey), September 58, 2012, pp. 368373. pdf
 P. Fišer and J. Schmidt, "Improving the Iterative Power of Resynthesis," in Proc. of 15th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Tallinn (Estonia), April 1820, 2012, pp. 3033. pdf
2011
 J. Balcárek, P. Fišer, and J. Schmidt, "Implicit Techniques for Constrained Test Patterns Generation," in Proc. of Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS), Lednice (ČR), October 1416, 2011, pp. 106.
 J. Balcárek, P. Fišer, and J. Schmidt, "Techniques for SATbased Constrained Test Pattern Generation," in Proc. of 14th Euromicro Conference on Digital Systems Design (DSD), Oulu (Finland), August 31September 2, 2011, pp. 360366. pdf
 P. Fišer and J. Schmidt, "How Much Randomness Makes a Tool Randomized?," in Proc. of 20th International Workshop on Logic and Synthesis 2011 (IWLS), San Diego, California (USA), June 35, 2011, pp. 136143. pdf, slides
 D. Toman and P. Fišer, "Using Ternary Trees in Logic Synthesis," in Proc of Workshop ČVUT, Prague, 2011, p. 15. pdf
2010
 D. Toman and P. Fišer, "A SOP Minimizer for Logic Functions Described by Many Product Terms Based on Ternary Trees," in Proc. of 9th Int. Workshop on Boolean Problems (IWSBP), Freiberg, Germany, September 1617, 2010, pp. 165172. pdf
 P. Fišer and J. Schmidt, "New Ways of Generating Large Realistic Benchmarks for Testing Synthesis Tools," in Proc. of 9th Int. Workshop on Boolean Problems (IWSBP), Freiberg, Germany, September 1617, 2010, pp. 157164. pdf, slides
 J. Balcárek, P. Fišer, and J. Schmidt, "Test Patterns Compression Technique Based on a Dedicated SATbased ATPG," in Proc. of 13th Euromicro Conference on Digital Systems Design (DSD), Lille (France), September 13, 2010, pp. 805808. pdf
 I. Lemberski and P. Fišer, "Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints," in Proc. of 13th Euromicro Conference on Digital Systems Design (DSD), Lille (France), September 13, 2010, pp. 155162. pdf, slides
 P. Fišer and J. Schmidt, "It Is Better to Run Iterative Resynthesis on Parts of the Circuit," in Proc. of 19th International Workshop on Logic and Synthesis 2010 (IWLS), Irvine, California (USA), June 1820, 2010, pp. 1724. pdf, slides
 J. Balcárek, P. Fišer, and J. Schmidt, "Implicit Representations in Test Patterns Compression for ScanBased Digital Circuits," in Proc. of Informal Proceedings of European Test Symposium (ETS), Prague (CR), May 2428, 2010.
 P. Fišer, J. Schmidt, Z. Vašíček, and L. Sekanina, "On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming," in Proc. of 13th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Vienna (Austria), April 1416, 2010, pp. 346351. pdf, slides
2009
 J. Balcárek, P. Fišer, and J. Schmidt, "On Properties of SAT Instances Produced by SATBased Test Pattern Generators," in Proc. of Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS), Znojmo, ČR, November 1315, 2009, pp. 310. pdf
 I. Lemberski and P. Fišer, "MultiLevel Implementation of Asynchronous Logic Using TwoLevel Nodes," in Proc. of 4th DescreteEvent System Design (DESDes), Gandia Beach, Valencia (Spain), August 68, 2009, pp. 213218. pdf, slides
 P. Fišer and J. Schmidt, "The Observed Role of Structure in Logic Synthesis Examples," in Proc. of 18th International Workshop on Logic and Synthesis 2009 (IWLS), Berkeley, California (USA), July 31August 2, 2009, pp. 210213. pdf
 P. Fišer and D. Toman, "A Fast SOP Minimizer for Logic Functions Described by Many Product Terms," in Proc. of 12th Euromicro Conference on Digital Systems Design (DSD), Patras (Greece), August 2729, 2009, pp. 757764. pdf
 P. Fišer and J. Schmidt, "The Case for a Balanced Decomposition Process," in Proc. of 12th Euromicro Conference on Digital Systems Design (DSD), Patras (Greece), August 2729, 2009, pp. 601604. pdf
 I. Lemberski and P. Fišer, "Asynchronous TwoLevel Logic of Reduced Cost," in Proc. of 12th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Liberec (ČR), April 1517, 2009, pp. 6873. pdf
2008
 P. Fišer and J. Schmidt, "Small but Nasty Logic Synthesis Examples," in Proc. of 8th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 1819, 2008, pp. 183190. pdf
 P. Fišer and D. Toman, "BoolTool: A Tool for Manipulation of Boolean Functions," in Proc. of 8th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 1819, 2008, pp. 109114. pdf, slides
 P. Fišer, P. Kubalík, and H. Kubátová, "An Efficient MultipleParity Generator Design for OnLine Testing on FPGA," in Proc. of of 11th Euromicro Conference on Digital Systems Design (DSD), Parma (Italy), 3.5.9.2008, pp. 9499. pdf
 P. Fišer and H. Kubátová, "ColumnMatching Based MixedMode Test Pattern Generator Design Technique for BIST," in Microprocessors and Microsystems journal, Dependability and Testing of Modern Digital Systems special issue, Elsevier, vol. 32, issues 56, August 2008, pp. 340350. pdf
 P. Fišer, P. Rucký, and I. Váňová, "Fast Boolean Minimizer for Completely Specified Functions," 11th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Bratislava (SK), April 1618, 2008, pp. 122127. pdf, slides
 P. Fišer and H. Kubátová, "Scalable Test Pattern Generator Design Method for BIST," in Proc. of 9th IEEE LatinAmerican Test Workshop (LATW), Puebla (Mexico), February 1720, 2008, pp. 6974. pdf, slides
2007
 P. Fišer, "ColumnMatching Based Mixed Mode Bist Technique," Ph.D. Thesis, Prague, CTU, June 2007, 94 p. pdf
 P. Fišer and H. Kubátová, "PseudoRandom Pattern Generator Design for ColumnMatching BIST," in Proc. of 10th Euromicro Conference on Digital Systems Design (DSD), Lübeck (Germany), July 2731, 2007, pp. 657663. pdf, slides
2006
 P. Fišer, P. Kubalík, and H. Kubátová, "Output Grouping Method Based on a Similarity of Boolean Functions," in Proc. of 7th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 2122, 2006, pp. 107113. pdf, slides
 P. Fišer and H. Kubátová, "Flexible TwoLevel Boolean Minimizer BOOM II and Its Applications," in Proc. of 9th Euromicro Conference on Digital Systems Design (DSD), Cavtat (Croatia), August 30September 1, 2006, pp. 369376. pdf, slides
 P. Kubalík, P. Fišer, and H. Kubátová, "Fault Tolerant System Design Method Based on SelfChecking Circuits," in Proc. of 12th International OnLine Testing Symposium (IOLTS), Lake of Como (Italy), July 1012, 2006, pp. 185186. pdf
 P. Fišer and H. Kubátová, "MultipleVector ColumnMatching BIST Design Method," in Proc. of 9th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Prague (CR), April 1821, 2006, pp. 268273. pdf, slides
2005
 P. Fišer, "MixedMode BIST Based on Column Matching," in Proc. of Počítačové Architektury & Diagnostika (PAD), Lázně Sedmihorky (CR), September 21–23, 2005, pp. 4550. pdf, slides
 P. Fišer and H. Kubátová, "Pseudorandom Testability  A Study of the Effect of the Generator Type," in Acta Polytechnica, Vol. 45, No. 2, August 2005, CVUT, pp. 4754. pdf
 P. Fišer and H. Kubátová, "Improvement of the Fault Coverage of the PseudoRandom Phase in Column Matching BIST," in Proc. of 31th Euromicro Symposium on Digital Systems Design (DSD), Porto, (Portugal), August 30September 3, 2005, pp. 5663. pdf, slides
 P. Fišer and H. Kubátová, "Output GroupingBased Decomposition of Logic Functions," in Proc. of 8th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Sopron (Hungary), April 1316, 2005, pp. 137144. pdf, slides
2004
 P. Fišer and H. Kubátová, "Influence of the Test Lengths on Area Overhead in MixedMode BIST," in Proc. of 9th Biennial Baltic Electronics Conference (BEC), Tallinn (Estonia), October 36, 2004, pp. 201204. pdf, slides
 P. Fišer and H. Kubátová, "Pseudorandom Testability, Study of the Effect of the Generator Type," in Proc. of International Scientific Conference Electronic Computers and Informatics (ECI), Herľany (SR), September 2224, 2004, pp. 200205. pdf, slides
 P. Fišer, "MixedMode BIST Based on Column Matching," Postgraduate Study Report, Prague, CTU, September 2004, 45 pp. pdf, slides
 P. Fišer and H. Kubátová, "TwoLevel Boolean Minimizer BOOMII," in Proc. of 6th Int. Workshop on Boolean Problems (IWSBP), Freiberg, Germany, September 2324, 2004, pp. 221228. pdf, slides
 P. Fišer and H. Kubátová, "SingleLevel Partitioning Support in BOOMII," in Proc. of 2nd DescreteEvent System Design (DESDes), Dychów (Poland), September 1517, 2004, pp. 149154. pdf, slides
 P. Kubalík, P. Fišer, and H. Kubátová, "Minimization of the Hamming Code Generator in Self Checking Circuits," in Proc. of 2nd DescreteEvent System Design (DESDes), Dychów (Poland), September 1517, 2004, pp. 161166. pdf
 P. Fišer and H. Kubátová, "Boolean Minimizer FCMin: Coverage Finding Process," in Proc. of 30th Euromicro Symposium on Digital Systems Design (DSD), Rennes (FR), August 31September 3, 04, pp. 152159. pdf, slides
 P. Fišer and H. Kubátová, "Survey of the Algorithms in the ColumnMatching BIST Method," in Proc. of 10th International OnLine Testing Symposium (IOLTS), Madeira (Portugal), July 1214, 2004, pp. 181. pdf, poster
 P. Fišer and H. Kubátová, "An Efficient MixedMode BIST Technique," in Proc. of 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Tatranská Lomnica (SK), April 1821, 2004, pp. 227230. pdf
2003
 P. Fišer and H. Kubátová, "The Iterative Boolean Minimizer FCMin", Pracovní seminář Počítačové Architektury & Diagnostika (PAD), Zvíkov (CR), September 2426, 2003, pp. 5762. pdf
 P. Fišer and J. Hlavička, "BOOM, A Heuristic Boolean Minimizer," in Computers and Informatics, Vol. 22, 2003, No. 1, pp. 1951. pdf
 P. Fišer, J. Hlavička, and H. Kubátová, "FCMin: A Fast MultiOutput Boolean Minimizer," in Proc. of 29th Euromicro Symposium on Digital Systems Design (DSD), Antalya (TR), September 16, 2003, pp. 451454. pdf
 P. Fišer, J. Hlavička, and H. Kubátová, "CDA Based BIST Method," in Proc. of 6th International Workshop on Electronics, Control, Measurement and Signals (ECMS), Liberec (CR), June 24, 2003, pp. 279283. pdf
 P. Fišer, J. Hlavička, and H. Kubátová, "ColumnMatching BIST Exploiting Test Don'tCares," in Proc. of 8th IEEE Europian Test Workshop (ETW), Maastricht (The Netherlands), May 2528, 2003, pp. 215216. pdf, poster
 P. Fišer, J. Hlavička, and H. Kubátová, "CoverageDirected Assignment Approach to BIST," in Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Poznan (Poland), April 1416, 2003, pp. 8792. pdf
 P. Fišer and J. Hlavička, "A Flexible Minimization and Partitioning Method," in Proc. of Workshop 2003, CTU, Prague, 2003, vol. A, pp. 312313.
2002
 P. Fišer, "Minimization of Boolean Functions," MSc. Thesis, Prague, CTU, May 2002, 70 p. pdf
 P. Fišer and J. Hlavička, "A Flexible Minimization and Partitioning Method," in Proc. of 5th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany) September 1920, 2002, pp. 8390. pdf, Powerpoint slides
 P. Fišer and J. Hlavička, "ColumnMatching Based BIST Design Method," in Proc. of 7th IEEE Europian Test Workshop (ETW), Corfu (Greece), May 2629, 2002, pp. 1516. pdf, poster
 P. Fišer and J. Hlavička, "A Set of Logic Design Benchmarks," in Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Brno (Czech Rep.), April 1719, 2002, pp. 324327. pdf
 J. Hlavička and P. Fišer, "Minimization and Partitioning Method Reducing Input Sets," in Proc. of the 1st International Workshop on Electronic Design, Test & Applications (DELTA), New Zealand, January 2931, 2002, pp. 434436.pdf
2001
 J. Hlavička and P. Fišer, "BOOM, a Heuristic Boolean Minimizer," in Proc. of International Conference on ComputerAided Design (ICCAD), San Jose, California (USA), November 48, 2001, pp. 439442. pdf
 P. Fišer and J. Hlavička, "BOOM, a Boolean Minimizer," Research Report DC200105, Prague, CTU Publishing House, June 2001, 37 pp. pdf
 P. Fišer and J. Hlavička, "On the Use of Mutations in Boolean Minimization," in Proc. of Euromicro Symposium on Digital Systems Design (DSD), Warsaw (Poland), September 46, 2001, pp. 300305. pdf
 J. Hlavička and P. Fišer, "A Heuristic method of twolevel logic synthesis," in Proc. of the 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI), Orlando, Florida (USA), July 2225, 2001, pp. 283288, vol. II. pdf
 P. Fišer and J. Hlavička, "Implicant Expansion Method used in the BOOM Minimizer," in Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'01), Gyor (Hungary), April 1820, 2001, pp. 291298. pdf, slides
2000
 P. Fišer and J. Hlavička, "Efficient minimization method for incompletely defined Boolean functions," in Proc. of 4th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 2122, 2000, pp.9198. pdf
 J. Hlavička and P. Fišer, "Algorithm for Minimization of Partial Boolean Functions," in Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Smolenice, (Slovakia), April 57, 2000, pp.130133. pdf
