Publications

2017
  • P. Fišer, I. Háleček, and J. Schmidt, "SAT-Based Generation of Optimum Function Implementations with XOR Gates", in Proc. of 20th Euromicro Conference on Digital Systems Design (DSD), Vienna, Austria, August 31-September 1, 2017, pp. 163-170. pdf
  • R. Hülle, P. Fišer, and J. Schmidt, "SAT-based ATPG for Zero-Aliasing Compaction", in Proc. of 20th Euromicro Conference on Digital Systems Design (DSD), Vienna, Austria, August 31-September 1, 2017, pp. 307-314. pdf
  • J. Bělohoubek, P. Fišer, and J. Schmidt, "Error Masking Method Based On The Short-Duration Offline Test," Microprocessors and Microsystems (MICPRO), Elsevier, vol. 52, July 2017, pp. 236-250. doi
  • I. Háleček, P. Fišer, J. Schmidt, "On XAIG Rewriting," in Proc. of 26th International Workshop on Logic & Synthesis (IWLS), Austin, TX, June 17 – 18, 2017, pp. 89-96. pdf
  • I. Háleček, P. Fišer, J. Schmidt, "Are XORs in logic synthesis really necessary?," in Proc. of IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Dresden (DE), April 19-21, 2017, pp. 138-143. pdf
2016
  • R. Hülle, P. Fišer, J. Schmidt, and J. Borecký, "SAT-ATPG for Application-Oriented FPGA Testing", in Proc. of the 15th Biennial Baltic Electronics Conference (BEC), October 3-5, 2016, Tallinn, Estonia, pp. 83-86. pdf
  • J. Schmidt and P. Fišer, "A Prudent Approach to Benchmark Collection," in Proc. of 12th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 22-23, 2016, pp. 129-136. pdf
  • P. Fišer and J. Schmidt, "A Comprehensive Set of Logic Synthesis and Optimization Examples," in Proc. of 12th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 22-23, 2016, pp. 151-158. pdf
  • J. Bělohoubek, P. Fišer, and J. Schmidt, "Error Correction Method Based on the Short-Duration Offline Test," in Proc. of 19th Euromicro Conference on Digital Systems Design (DSD), Limassol, Cyprus, August 31-September 2, 2016, pp. 495-502. pdf
  • J. Schmidt, R. B. Blažek, and P. Fišer, "Towards Understanding the Performance of Randomized Algorithms", in Problems and New Solutions in the Boolean Domain (book chapter), May 2016, pp. 167-186.
  • R. Tamáši, M. Siebert, P. Fišer, and E. Gramatová, "A New Method for Path Criticality Calculation," in Proc. of IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice (SK), April 20-22, 2016, pp. 190-193. pdf
  • M. Lipovský, J. Švarc, E. Gramatová, and P. Fišer, "A New User-Friendly ATPG Platform for Digital Circuits," in Proc. of IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice (SK), April 20-22, 2016, pp. 210-213. pdf
  • S. Das, P. Dasgupta, P. Fišer, S. Ghosh, D. K. Das, "A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits," in Proc. of IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice (SK), April 20-22, 2016, pp. 237-242. pdf
2015
  • I. Háleček, P. Fišer, and J. Schmidt, "On Identification of XOR Gates in AIGs," in Proc. of the Work in Progress Session of the 18th Euromicro Conference on Digital Systems Design (DSD), Fuchal, Madeira, Portugal, August 26-28, 2015, 2 p. pdf
  • J. Bělohoubek, P. Fišer, and J. Schmidt, "Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy," in Proc. of 18th Euromicro Conference on Digital Systems Design (DSD), Fuchal, Madeira, Portugal, August 26-28, 2015, pp. 280-283. pdf
  • R. Tamaši, M. Siebert, and P. Fišer, "A New Method for Specification of Parameters to Path Delay Faults Testing," in Proc. of the 3rd Prague Embedded Systems Workshop (PESW), July 2-4, 2015, Roztoky u Prahy (Czech Rep.), pp. 26-32. pdf
  • P. Fišer and J. Schmidt, "Introduction to Lethal Circuit Transformations," in Proc. of Design and Analysis of Control Systems, March 20-23, 2015, Athens, Greece, p. 4. pdf
2014
  • P. Fišer and J. Schmidt, "The Logic Synthesis Homework Is Not Done Yet", invited talk at 10th Italian Annual Seminar Day on Logic Synthesis. slides
  • J. Balcárek, P. Fišer, and J. Schmidt, "On Don’t Cares in Test Compression", Microprocessors and Microsystems (MICPRO), Elsevier, Volume 38, Issue 8, Part A, November 2014, pp. 754–765. pdf, doi
  • J. Schmidt, R. Blažek, and P. Fišer, "On Probability Density Distribution of Randomized Algorithms Performance," in Proc. of 11th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 17-19, 2014, pp. 67-74. pdf
  • P. Fišer, J. Schmidt, and J. Balcárek, "On Robustness of EDA Tools," in Proc. of 17th Euromicro Conference on Digital Systems Design (DSD), Verona (Italy), August 27-29, 2014, pp. 427-434. pdf
  • J. Balcárek, P. Fišer, and J. Schmidt, "PBO-Based Test Compression," in Proc. of 17th Euromicro Conference on Digital Systems Design (DSD), Verona (Italy), August 27-29, 2014, pp. 679-682. pdf
  • I. Lemberski, P. Fišer, and R. Suleimanov, "Asynchronous sum-of-products logic minimization and orthogonalization," in International Journal of Circuit Theory and Applications, John Wiley & Sons, Ltd., Vol. 42, Issue 6, June 2014, pp. 562–571. doi
  • P. Fišer and J. Schmidt, "Permuting Variables to Improve Iterative Resynthesis," in Recent Progress in the Boolean Domain (book chapter), April 2014, pp. 213-230.
  • A. Bernasconi, V. Ciriani, P. Fišer, and G. Trucco, "Weighted Don't Cares in Logic Synthesis," in Recent Progress in the Boolean Domain (book chapter), April 2014, pp. 263-277.
  • P. Fišer, J. Schmidt, and J. Balcárek, "Sources of Bias in EDA Tools and Its Influence," in Proc. of 17th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Warsaw (Poland), April 23-25, 2014, pp. 258-261. pdf
  • I. Lemberski and P. Fišer, "Dual-Rail Asynchronous Logic Multi-Level Implementation," in Integration, the VLSI Journal, Elsevier, vol. 47, Issue 1, January 2014, pp. 148–159. pdf, doi
2013
  • J. Schmidt, P. Fišer, J. Balcárek, "The influence of implementation type on dependability parameters", Microprocessors and Microsystems (MICPRO), Vol. 37, Issue 6-7, August-October 2013, Elsevier, pp. 641-648. pdf, doi
  • Jan Pospíšil, Jan Schmidt, Petr Fišer, "New SEU Modeling by Architecture Analysis," in Proc. Work in Progress Session of 16th Euromicro Conference on Digital Systems Design (DSD), Santander (Spain), September 4-6, 2013.
  • J. Balcárek, P. Fišer, and J. Schmidt, "Simulation and SAT Based ATPG for Compressed Test Generation," in Proc. of 16th Euromicro Conference on Digital Systems Design (DSD), Santander (Spain), September 4-6, 2013, pp. 445-452. pdf
  • J. Balcárek, P. Fišer, and J. Schmidt, "Techniques for SAT-based Constrained Test Pattern Generation," in Microprocessors and Microsystems (MICPRO), Vol. 37, Issue 2, March 2013, Elsevier, pp. 185-195. pdf, doi
2012
  • P. Fišer, "Randomized Iterative Logic Synthesis Algorithms," Habilitation Thesis, Brno, 2012, p. 84.
  • J. Schmidt, P. Fišer and J. Balcárek, "Generalized Miter and its Application in Hardware Design," in Proc. of the 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS), Znojmo (ČR), October 25-28, 2012, pp. 119-120.
  • P. Fišer and J. Schmidt, "On Using Permutation of Variables to Improve the Iterative Power of Resynthesis," in Proc. of 10th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 19-21, 2012, pp. 107-114. pdf
  • P. Fišer and J. Schmidt, "A Difficult Example Or a Badly Represented One?," in Proc. of 10th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 19-21, 2012, pp. 115-122. pdf
  • A. Bernasconi, V. Ciriani, P. Fišer, and G. Trucco, "Weighted Don't Cares," in Proc. of 10th Int. Workshop on Boolean Problems (IWSBP), Freiberg, (Germany), September 19-21, 2012, pp. 123-130. pdf
  • J. Schmidt, P. Fišer and J. Balcárek, "The Influence of Implementation Technology on Dependability Parameters," in Proc. of 15th Euromicro Conference on Digital Systems Design (DSD), Cesme (Turkey), September 5-8, 2012, pp. 368-373. pdf
  • P. Fišer and J. Schmidt, "Improving the Iterative Power of Resynthesis," in Proc. of 15th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Tallinn (Estonia), April 18-20, 2012, pp. 30-33. pdf
2011
  • J. Balcárek, P. Fišer, and J. Schmidt, "Implicit Techniques for Constrained Test Patterns Generation," in Proc. of Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS), Lednice (ČR), October 14-16, 2011, pp. 106.
  • J. Balcárek, P. Fišer, and J. Schmidt, "Techniques for SAT-based Constrained Test Pattern Generation," in Proc. of 14th Euromicro Conference on Digital Systems Design (DSD), Oulu (Finland), August 31-September 2, 2011, pp. 360-366. pdf
  • P. Fišer and J. Schmidt, "How Much Randomness Makes a Tool Randomized?," in Proc. of 20th International Workshop on Logic and Synthesis 2011 (IWLS), San Diego, California (USA), June 3-5, 2011, pp. 136-143. pdf, slides
  • D. Toman and P. Fišer, "Using Ternary Trees in Logic Synthesis," in Proc of Workshop ČVUT, Prague, 2011, p. 15. pdf
2010
  • D. Toman and P. Fišer, "A SOP Minimizer for Logic Functions Described by Many Product Terms Based on Ternary Trees," in Proc. of 9th Int. Workshop on Boolean Problems (IWSBP), Freiberg, Germany, September 16-17, 2010, pp. 165-172. pdf
  • P. Fišer and J. Schmidt, "New Ways of Generating Large Realistic Benchmarks for Testing Synthesis Tools," in Proc. of 9th Int. Workshop on Boolean Problems (IWSBP), Freiberg, Germany, September 16-17, 2010, pp. 157-164. pdf, slides
  • J. Balcárek, P. Fišer, and J. Schmidt, "Test Patterns Compression Technique Based on a Dedicated SAT-based ATPG," in Proc. of 13th Euromicro Conference on Digital Systems Design (DSD), Lille (France), September 1-3, 2010, pp. 805-808. pdf
  • I. Lemberski and P. Fišer, "Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints," in Proc. of 13th Euromicro Conference on Digital Systems Design (DSD), Lille (France), September 1-3, 2010, pp. 155-162. pdf, slides
  • P. Fišer and J. Schmidt, "It Is Better to Run Iterative Resynthesis on Parts of the Circuit," in Proc. of 19th International Workshop on Logic and Synthesis 2010 (IWLS), Irvine, California (USA), June 18-20, 2010, pp. 17-24. pdf, slides
  • J. Balcárek, P. Fišer, and J. Schmidt, "Implicit Representations in Test Patterns Compression for Scan-Based Digital Circuits," in Proc. of Informal Proceedings of European Test Symposium (ETS), Prague (CR), May 24-28, 2010.
  • P. Fišer, J. Schmidt, Z. Vašíček, and L. Sekanina, "On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming," in Proc. of 13th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Vienna (Austria), April 14-16, 2010, pp. 346-351. pdf, slides
2009
  • J. Balcárek, P. Fišer, and J. Schmidt, "On Properties of SAT Instances Produced by SAT-Based Test Pattern Generators," in Proc. of Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS), Znojmo, ČR, November 13-15, 2009, pp. 3-10. pdf
  • I. Lemberski and P. Fišer, "Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes," in Proc. of 4th Descrete-Event System Design (DESDes), Gandia Beach, Valencia (Spain), August 6-8, 2009, pp. 213-218. pdf, slides
  • P. Fišer and J. Schmidt, "The Observed Role of Structure in Logic Synthesis Examples," in Proc. of 18th International Workshop on Logic and Synthesis 2009 (IWLS), Berkeley, California (USA), July 31-August 2, 2009, pp. 210-213. pdf
  • P. Fišer and D. Toman, "A Fast SOP Minimizer for Logic Functions Described by Many Product Terms," in Proc. of 12th Euromicro Conference on Digital Systems Design (DSD), Patras (Greece), August 27-29, 2009, pp. 757-764. pdf
  • P. Fišer and J. Schmidt, "The Case for a Balanced Decomposition Process," in Proc. of 12th Euromicro Conference on Digital Systems Design (DSD), Patras (Greece), August 27-29, 2009, pp. 601-604. pdf
  • I. Lemberski and P. Fišer, "Asynchronous Two-Level Logic of Reduced Cost," in Proc. of 12th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Liberec (ČR), April 15-17, 2009, pp. 68-73. pdf
2008
  • P. Fišer and J. Schmidt, "Small but Nasty Logic Synthesis Examples," in Proc. of 8th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 18-19, 2008, pp. 183-190. pdf
  • P. Fišer and D. Toman, "BoolTool: A Tool for Manipulation of Boolean Functions," in Proc. of 8th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 18-19, 2008, pp. 109-114. pdf, slides
  • P. Fišer, P. Kubalík, and H. Kubátová, "An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA," in Proc. of of 11th Euromicro Conference on Digital Systems Design (DSD), Parma (Italy), 3.-5.9.2008, pp. 94-99. pdf
  • P. Fišer and H. Kubátová, "Column-Matching Based Mixed-Mode Test Pattern Generator Design Technique for BIST," in Microprocessors and Microsystems journal, Dependability and Testing of Modern Digital Systems special issue, Elsevier, vol. 32, issues 5-6, August 2008, pp. 340-350. pdf
  • P. Fišer, P. Rucký, and I. Váňová, "Fast Boolean Minimizer for Completely Specified Functions," 11th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Bratislava (SK), April 16-18, 2008, pp. 122-127. pdf, slides
  • P. Fišer and H. Kubátová, "Scalable Test Pattern Generator Design Method for BIST," in Proc. of 9th IEEE Latin-American Test Workshop (LATW), Puebla (Mexico), February 17-20, 2008, pp. 69-74. pdf, slides
2007
  • P. Fišer, "Column-Matching Based Mixed Mode Bist Technique," Ph.D. Thesis, Prague, CTU, June 2007, 94 p. pdf
  • P. Fišer and H. Kubátová, "Pseudo-Random Pattern Generator Design for Column-Matching BIST," in Proc. of 10th Euromicro Conference on Digital Systems Design (DSD), Lübeck (Germany), July 27-31, 2007, pp. 657-663. pdf, slides
2006
  • P. Fišer, P. Kubalík, and H. Kubátová, "Output Grouping Method Based on a Similarity of Boolean Functions," in Proc. of 7th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 21-22, 2006, pp. 107-113. pdf, slides
  • P. Fišer and H. Kubátová, "Flexible Two-Level Boolean Minimizer BOOM II and Its Applications," in Proc. of 9th Euromicro Conference on Digital Systems Design (DSD), Cavtat (Croatia), August 30-September 1, 2006, pp. 369-376. pdf, slides
  • P. Kubalík, P. Fišer, and H. Kubátová, "Fault Tolerant System Design Method Based on Self-Checking Circuits," in Proc. of 12th International On-Line Testing Symposium (IOLTS), Lake of Como (Italy), July 10-12, 2006, pp. 185-186. pdf
  • P. Fišer and H. Kubátová, "Multiple-Vector Column-Matching BIST Design Method," in Proc. of 9th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), Prague (CR), April 18-21, 2006, pp. 268-273. pdf, slides
2005
  • P. Fišer, "Mixed-Mode BIST Based on Column Matching," in Proc. of Počítačové Architektury & Diagnostika (PAD), Lázně Sedmihorky (CR), September 21–23, 2005, pp. 45-50. pdf, slides
  • P. Fišer and H. Kubátová, "Pseudorandom Testability - A Study of the Effect of the Generator Type," in Acta Polytechnica, Vol. 45, No. 2, August 2005, CVUT, pp. 47-54. pdf
  • P. Fišer and H. Kubátová, "Improvement of the Fault Coverage of the Pseudo-Random Phase in Column Matching BIST," in Proc. of 31th Euromicro Symposium on Digital Systems Design (DSD), Porto, (Portugal), August 30-September 3, 2005, pp. 56-63. pdf, slides
  • P. Fišer and H. Kubátová, "Output Grouping-Based Decomposition of Logic Functions," in Proc. of 8th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Sopron (Hungary), April 13-16, 2005, pp. 137-144. pdf, slides
2004
  • P. Fišer and H. Kubátová, "Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST," in Proc. of 9th Biennial Baltic Electronics Conference (BEC), Tallinn (Estonia), October 3-6, 2004, pp. 201-204. pdf, slides
  • P. Fišer and H. Kubátová, "Pseudorandom Testability, Study of the Effect of the Generator Type," in Proc. of International Scientific Conference Electronic Computers and Informatics (ECI), Herľany (SR), September 22-24, 2004, pp. 200-205. pdf, slides
  • P. Fišer, "Mixed-Mode BIST Based on Column Matching," Postgraduate Study Report, Prague, CTU, September 2004, 45 pp. pdf, slides
  • P. Fišer and H. Kubátová, "Two-Level Boolean Minimizer BOOM-II," in Proc. of 6th Int. Workshop on Boolean Problems (IWSBP), Freiberg, Germany, September 23-24, 2004, pp. 221-228. pdf, slides
  • P. Fišer and H. Kubátová, "Single-Level Partitioning Support in BOOM-II," in Proc. of 2nd Descrete-Event System Design (DESDes), Dychów (Poland), September 15-17, 2004, pp. 149-154. pdf, slides
  • P. Kubalík, P. Fišer, and H. Kubátová, "Minimization of the Hamming Code Generator in Self Checking Circuits," in Proc. of 2nd Descrete-Event System Design (DESDes), Dychów (Poland), September 15-17, 2004, pp. 161-166. pdf
  • P. Fišer and H. Kubátová, "Boolean Minimizer FC-Min: Coverage Finding Process," in Proc. of 30th Euromicro Symposium on Digital Systems Design (DSD), Rennes (FR), August 31-September 3, 04, pp. 152-159. pdf, slides
  • P. Fišer and H. Kubátová, "Survey of the Algorithms in the Column-Matching BIST Method," in Proc. of 10th International On-Line Testing Symposium (IOLTS), Madeira (Portugal), July 12-14, 2004, pp. 181. pdf, poster
  • P. Fišer and H. Kubátová, "An Efficient Mixed-Mode BIST Technique," in Proc. of 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Tatranská Lomnica (SK), April 18-21, 2004, pp. 227-230. pdf
2003
  • P. Fišer and H. Kubátová, "The Iterative Boolean Minimizer FC-Min", Pracovní seminář Počítačové Architektury & Diagnostika (PAD), Zvíkov (CR), September 24-26, 2003, pp. 57-62. pdf
  • P. Fišer and J. Hlavička, "BOOM, A Heuristic Boolean Minimizer," in Computers and Informatics, Vol. 22, 2003, No. 1, pp. 19-51. pdf
  • P. Fišer, J. Hlavička, and H. Kubátová, "FC-Min: A Fast Multi-Output Boolean Minimizer," in Proc. of 29th Euromicro Symposium on Digital Systems Design (DSD), Antalya (TR), September 1-6, 2003, pp. 451-454. pdf
  • P. Fišer, J. Hlavička, and H. Kubátová, "CD-A Based BIST Method," in Proc. of 6th International Workshop on Electronics, Control, Measurement and Signals (ECMS), Liberec (CR), June 2-4, 2003, pp. 279-283. pdf
  • P. Fišer, J. Hlavička, and H. Kubátová, "Column-Matching BIST Exploiting Test Don't-Cares," in Proc. of 8th IEEE Europian Test Workshop (ETW), Maastricht (The Netherlands), May 25-28, 2003, pp. 215-216. pdf, poster
  • P. Fišer, J. Hlavička, and H. Kubátová, "Coverage-Directed Assignment Approach to BIST," in Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Poznan (Poland), April 14-16, 2003, pp. 87-92. pdf
  • P. Fišer and J. Hlavička, "A Flexible Minimization and Partitioning Method," in Proc. of Workshop 2003, CTU, Prague, 2003, vol. A, pp. 312-313.
2002
  • P. Fišer, "Minimization of Boolean Functions," MSc. Thesis, Prague, CTU, May 2002, 70 p. pdf
  • P. Fišer and J. Hlavička, "A Flexible Minimization and Partitioning Method," in Proc. of 5th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany) September 19-20, 2002, pp. 83-90. pdf, Powerpoint slides
  • P. Fišer and J. Hlavička, "Column-Matching Based BIST Design Method," in Proc. of 7th IEEE Europian Test Workshop (ETW), Corfu (Greece), May 26-29, 2002, pp. 15-16. pdf, poster
  • P. Fišer and J. Hlavička, "A Set of Logic Design Benchmarks," in Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Brno (Czech Rep.), April 17-19, 2002, pp. 324-327. pdf
  • J. Hlavička and P. Fišer, "Minimization and Partitioning Method Reducing Input Sets," in Proc. of the 1st International Workshop on Electronic Design, Test & Applications (DELTA), New Zealand, January 29-31, 2002, pp. 434-436.pdf
2001
  • J. Hlavička and P. Fišer, "BOOM, a Heuristic Boolean Minimizer," in Proc. of International Conference on Computer-Aided Design (ICCAD), San Jose, California (USA), November 4-8, 2001, pp. 439-442. pdf
  • P. Fišer and J. Hlavička, "BOOM, a Boolean Minimizer," Research Report DC-2001-05, Prague, CTU Publishing House, June 2001, 37 pp. pdf
  • P. Fišer and J. Hlavička, "On the Use of Mutations in Boolean Minimization," in Proc. of Euromicro Symposium on Digital Systems Design (DSD), Warsaw (Poland), September 4-6, 2001, pp. 300-305. pdf
  • J. Hlavička and P. Fišer, "A Heuristic method of two-level logic synthesis," in Proc. of the 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI), Orlando, Florida (USA), July 22-25, 2001, pp. 283-288, vol. II. pdf
  • P. Fišer and J. Hlavička, "Implicant Expansion Method used in the BOOM Minimizer," in Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'01), Gyor (Hungary), April 18-20, 2001, pp. 291-298. pdf, slides
2000
  • P. Fišer and J. Hlavička, "Efficient minimization method for incompletely defined Boolean functions," in Proc. of 4th Int. Workshop on Boolean Problems (IWSBP), Freiberg (Germany), September 21-22, 2000, pp.91-98. pdf
  • J. Hlavička and P. Fišer, "Algorithm for Minimization of Partial Boolean Functions," in Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Smolenice, (Slovakia), April 5-7, 2000, pp.130-133. pdf