Research Links

My Projects Available to Publics

Logic synthesis

BOOM - Two-level Boolean minimizer
TT-Min - Another two-level Boolean minimizer
BoolTool - The Boolean function manipulation tool
Resynth - Circuit resynthesis by parts
XorDecomp - A XOR decomposition tool
ABC Tcl - Tcl/Tk support for ABC
BDS - BDD-based decomposition tool, new version maintained by DDD

Diagnostics, testing

SAT-Compress - SAT-based ATPG tool
Fault classifier - classifies faults in circuits inplemented in ASIC or FPGA
ColMatch - A BIST design tool
TG-Pro - A SAT-based ATPG System


BOOM Benchmarks - A set of artificial BOOM benchmarks
Random Circuits Generators - Parametrized generators of random PLA and KISS files
A Collection of Digital Design Benchmarks (ISCAS, ITC, MCNC, IWLS, LGSynth, ...)
Logic Synthesis
ABC - Logic Synthesis Package from Berkeley
Berkeley CAD software
Berkeley - Center For Electronic Systems Design
BDS - A BDD-Based Logic Optimization System. The original version from UMASS.
BDS-pga - A BDD-Based FPGA mapper
CUDD - Colorado University Binary Decision Diagrams Software Package
BBDD package - Biconditional Binary Decision Diagrams Software Package
Exorcism - ESOP synthesis tool
Testing & Diagnostics
IGATE Illinois - ATPG Tools, tests for benchmarks
DefGen - ATPG
Atalanta, FSIM, HOPE - ATPG, fault simulators
Asynchronous Design
Papers, Publications