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software:software_down [2013/03/26 09:44]
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 ^  2010  |  PC  |  Linux and Cisco virtual network simulator ​  ​| ​ This application is the simulator composed of cisco and linux based routers. Simulator allows configuration of routers via Cisco IOS and Linux command line. Simulator implements commands for configuring interfaces, static routing, dynamic and static network address translation. This system also offers verification of current configuration via ping and traceroute commands. Entire network settings are loaded from a configuration file and there is also possibility to save current configuration to a given file. User testing is integral part of a work.  |  {{:​software:​simulator_linux.zip|zip}} ​ |  {{:​project:​2010:​2010_rehak_stanislav.pdf|pdf}} ​ | ^  2010  |  PC  |  Linux and Cisco virtual network simulator ​  ​| ​ This application is the simulator composed of cisco and linux based routers. Simulator allows configuration of routers via Cisco IOS and Linux command line. Simulator implements commands for configuring interfaces, static routing, dynamic and static network address translation. This system also offers verification of current configuration via ping and traceroute commands. Entire network settings are loaded from a configuration file and there is also possibility to save current configuration to a given file. User testing is integral part of a work.  |  {{:​software:​simulator_linux.zip|zip}} ​ |  {{:​project:​2010:​2010_rehak_stanislav.pdf|pdf}} ​ |
 ^  2011  |  Xilinx ML401 FPGA board  |  High speed ethernet core   ​| ​ This software realizes the fast ethernet core, which operates at 10, 100 and 1000 Mbps. The core is written in the VHDL language and the main property is the low latency, minimal space requirements and simplicity. Further usage of this score is in school projects instead of using commercial one (e. g. TEMAC). Because of previous reasons, there are implemented a subset of the IEEE 802.3 standard, which provides a functionality at 10, 100 and 1000 Mbps speeds with full duplex. ​ |  {{:​software:​high_speed_eth_core.zip|zip}} ​ |  {{:​project:​2011:​2011_dostal_jiri.pdf|pdf}} ​ | ^  2011  |  Xilinx ML401 FPGA board  |  High speed ethernet core   ​| ​ This software realizes the fast ethernet core, which operates at 10, 100 and 1000 Mbps. The core is written in the VHDL language and the main property is the low latency, minimal space requirements and simplicity. Further usage of this score is in school projects instead of using commercial one (e. g. TEMAC). Because of previous reasons, there are implemented a subset of the IEEE 802.3 standard, which provides a functionality at 10, 100 and 1000 Mbps speeds with full duplex. ​ |  {{:​software:​high_speed_eth_core.zip|zip}} ​ |  {{:​project:​2011:​2011_dostal_jiri.pdf|pdf}} ​ |
-^  2012  |  PC  |  Simple translator from C to VHDL language ​  ​| ​ This application can be used as a simple translator from C to microcode. C language allows using basic set of c command and simple synchronization commands. The result of the translation process is a microcontroller described by VHDL language. Application was written in Java language. ​ |  ​ ​|  ​ | +^  2012  |  PC  |  Simple translator from C to VHDL language ​  ​| ​ This application can be used as a simple translator from C to microcode. C language allows using basic set of c command and simple synchronization commands. The result of the translation process is a microcontroller described by VHDL language. Application was written in Java language. ​ |  ​{{:​software:​translator.zip|zip}} ​ ​|  ​{{:​project:​2012:​2012_brom_jiri.pdf|pdf}} ​ | 
-^  2012  |  PC  |  Design tool for VHDL code generation and project management ​ |  This application can be used as an development tool for VHDL code generation and project management (VHDT). The application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform was used as a basis for the implementation. ​ |  ​ ​|  ​ |+^  2012  |  PC  |  Design tool for VHDL code generation and project management ​ |  This application can be used as an development tool for VHDL code generation and project management (VHDT). The application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform was used as a basis for the implementation. ​ |  ​{{:​software:​vhdt_v1.613.zip|zip}} ​ ​|  ​{{:​project:​2012:​2012_mateju_jan.pdf|pdf}} ​ |
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software/software_down.1364287465.txt.gz · Last modified: 2013/03/26 09:44 by xkubalik