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====== All publications ======

==== 2017 ====

  * **Design of a Residue Number System Based Linear System Solver in Hardware**, Buček, J.; Kubalík, P.; Lórencz, R.; Zahradnický, T., Journal of Signal Processing Systems. 2016, 1-14. ISSN 1939-8018.


==== 2016 ====



  * **A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time**, Bartík, M.; Ubik, S.; Kubalík, P., In: ReConFig’16. Piscataway: IEEE, 2016, ISBN 978-1-5090-3706-3.
  * **Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase**, Bartík, M.; Ubik, S.; Kubalík, P., In: Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016, pp. 89-92. ISBN 978-80-214-5376-0.


==== 2015 ====

  * **LZ4 Compression Algorithm on FPGA**, Bartík, M., S. Ubik, and P. Kubalík, 21st IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, 2015-12-06/2015-12-09. New York: Institute of Electrical and Electronics Engineers, 2015, vol. 1, pp. 179-182. ISBN 978-1-4799-2451-6.
  * **Rychlé bezztrátové kompresní algoritmy**,	Bartík, M., S. Ubik, and P. Kubalík, Sborník příspěvků PAD 2015. Počítačové architektury a diagnostika 2015, Zlín, 2015-09-02/2015-09-04. Zlín: Universita Tomáše Bati ve Zlíně, 2015, pp. 31-36. ISBN 978-80-7454-522-1.
  * 
==== 2014 ====

  * **System Design of an FPGA Linear Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design, DSD2014, Verona, 2014-08-27/2014-08-29. Linz: Johannes Kepler University, 2014, ISBN 978-3-902457-40-0. {{ :publication:dsd14_wip.pdf |pdf}}
  * **System on Chip Design of a Linear System Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R.,. In: 2014 International Symposium on System-on-Chip Proceedings, SoC 2014, Tampere, 2014-10-28/2014-10-29. Piscataway: IEEE, 2014, ISBN 9781479968909. {{ :publication:soc14.pdf |pdf}}
  * **An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R., Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems, ICECS 2014, Marseille, 2014-12-07/2014-12-10. Monterey: IEEE Circuits and Systems Society, 2014, pp. 706-709. ISBN 978-1-4799-4242-8. {{ :publication:icecs14.pdf |pdf}}

==== 2013 ====

  * **Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R., Proceedings of 16th Euromicro Conference on Digital System Design, DSD 2013, pp.(284-287). {{:publication:dsd2013.pdf|pdf}}

==== 2012 ====

  * **Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R., Proceedings of the  19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, pp.(689-692). {{:publication:icecs2012.pdf|pdf}}

==== 2011 ====

  * **Fault-tolerant and fail-safe design based on reconfiguration**, Kubátová,H., Kubalík, P., Chapter in book: Design and Test Technology for Dependable Systems-on-Chip,  2011, pp.(175-194)
  * **Fault Models Usability Study for On-line Tested FPGA**, Borecký,J., Kohlík,M., Kubátová,H., Kubalík, P., Proceedings of the 13th Euromicro Conference on Digital System Design, Oulu, 2011, pp.(287-290) {{:publication:dsd2011.pdf|pdf}}
    * //__Citation__: **"A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip"**, Cédric Killian, Camel Tanougast, Fabrice Monteiro, and Abbas Dandache, Journal of Electrical and Computer Engineering, vol. 2012, Article ID 843239, 16 pages, 2012. doi:10.1155/2012/843239.//
    * //__Citation__: **"Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip"**, Eghbal, A.; Yaghini, P.M.; Bagherzadeh, N.; Khayambashi, M., Computers, IEEE Transactions on, vol. 64, pp. 3591 - 3604, 2015.//
    * //__Citation__: **"DAO: Dual module redundancy with AND/OR logic voter for FPGA hardening"**, Meisong Zheng; Zilong Wang; Lijian Li, Reliability Systems Engineering (ICRSE), 2015 First International Conference on, pp. 1 - 5, 2015.//
==== 2010 ====

  * **Faults Coverage Improvement based on Fault Simulation and Partial Duplication**, Borecký,J., Kohlík,M., Kubátová,H., Kubalík, P., Proceedings of the 13th Euromicro Conference on Digital System Design, Lille, 2010, pp.(380-386) {{:publication:dsd2010.pdf|pdf}}

==== 2009 ====

  * **Reliable Railway Station System based on Regular Structure implemented in FPGA**, Borecký,J., Kubalík,P., Kubátová,H, Proc. of 12th EUROMICRO Conference on Digital System Design, Patras, 2009, pp.(348-354). {{:publication:dsd2009.pdf|pdf}}
    * //__Citation__: **"Simulated Injection of Radiation-Induced Logic Faults in FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici,Giancarlo Gennaro, Mario Pasquariello;, The Third International Conference on Advances in System Testing and Validation Lifecycle, pp.84-89, VALID 2011//
    * //__Citation__: **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici,  Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621//
    * //__Citation__: **"Safety Automata Network for Interlocking System"**, Trifonov, V.,:  Mechanics Transport Communications, Academic journal, 2011.//
    * //__Citation__: **"Modern methods in railway interlocking algorithms design"**, Piotr Kawaleca, Marcin Rżysko, Microprocessors and Microsystems, 2015. ISSN 0141-9331.//
    * //__Citation__: **"Algorithms and hardware description languages in railway interlocking logic design"**, Piotr Kawalec, Marcin Rżysko, 13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems &#8212; PDES 2015, vol. 48, no. 4, pp. 498 - 503, 2015.//
==== 2008 ====

  * **Dependable design technique for system-on-chip** (Článek) 2008, KUBALÍK P., KUBÁTOVÁ H. Journal of Systems Architecture. 2008, vol. 2008, no. 54, p. 452-464. ISSN 1383-7621.
    * //__Citation__: **"Soft core based embedded systems in critical aerospace applications"**, Sergio Cuenca-Asensia, Antonio Martínez-Álvareza, Felipe Restrepo-Callea, Francisco R. Palomob, Hipólito Guzmán-Mirandab, Miguel A. Aguirreb;, Journal of Systems Architecture, vol.57, issue 10, no.0, pp.886-895, November 2011// 
    * //__Citation__: **"Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms"**, Cristiana Bolchini, Antonio Miele, Chiara Sandionigi;, Journal of Electronic Testing, vol.29, issue 6, no., pp.779-793, December 2013// 
    * //__Citation__: **"Soft Error Mitigation in Soft-Core Processors"**, A Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle, FPGAs and Parallel Architectures for Aerospace Applications, vol. Chapter 16, 2016. ISBN 9783319143521.//


  * **An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA** (Stať ve sborníku) 2008, FIŠER P., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2008, p. 96-99. ISBN 978-0-7695-3277-6. {{:publication:dsd2008_fiser.pdf|pdf}}
  * **Experimental SEU Impact on Digital Design Implemented in FPGAs** (Stať ve sborníku) 2008, KVASNIČKA J., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2008, p. 100-103. ISBN 978-0-7695-3277-6. {{:publication:dsd2008_kvasnicka.pdf|pdf}}
  * **Experimental emulation of FPGA bitstream faults in combinatorial circuits** (Stať v elektronickém sborníku) 2008, KVASNIČKA J., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of CSE 2008 International Scientific Conference on Computer Science and Engineering [CD-ROM]. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2008, vol. 1, p. 328-335. ISBN 978-80-8086-092-9. {{:publication:cse2008.pdf|pdf}}
==== 2007 ====

  * **Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System** (Stať ve sborníku) 2007, KUBALÍK P., KVASNIČKA J., KUBÁTOVÁ H. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 357-360. ISBN 1-4244-1161-0. {{:publication:ddecs2007.pdf|pdf}}
    * //__Citation__: **"Speeding up Fault Simulation using Parallel Fault Simulation"**, Jiahua Fan and Zhifeng Zhang;, Procedia Engineering, Elsevier, vol.15, no.0, pp.1817-1821, CEIS 2011// 

  * **An FPGA based fault emulator** (Stať ve sborníku) 2007, KVASNIČKA J., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007. Linz: Johannes Kepler University, 2007, p. 42-43. ISBN 978-3-902457-16-5. {{:publication:dsd2007.pdf|pdf}}
  * **Design of Self Checking Circuits Based on FPGAs** (Dissertation thesis (Ph.D.)) 2007, KUBALÍK P. [PhD Thesis]. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2007. 71 p. {{:publication:disert2007.pdf|pdf}}
==== 2006 ====

  * **Fault Tolerant System Design Method Based on Self-Checking Circuits** (Stať ve sborníku) 2006, KUBALÍK P., FIŠER P., KUBÁTOVÁ H. In Proceedings IOLTS 2006 12th IEEE International On-Line Testing Symposium, IOLTS2006. Los Alamitos: IEEE Computer Society, 2006, p. 185-186. ISBN 0-7695-2620-9. {{:publication:iolts2006.pdf|pdf}}
    * //__Citation__: **"Centralized Traffic Controlling System for Sri Lanka Railways"**, Ambegoda, A.L.A.T.D.; De Silva, W.T.S.; Hemachandra, K.T.; Samarasinghe, T.N.; Samarasinghe, A.T.L.K.;, Information and Automation for Sustainability, 2008. ICIAFS 2008. 4th International Conference on , vol., no., pp.145-149, 12-14 Dec. 2008//
    * //__Citation__: **"Digital Systems Architectures Based on On-line Checkers"**, Straka, M.; Kotasek, Z.; Winter, J.;, Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on , vol., no., pp.81-87, 3-5 Sept. 2008//
    * //__Citation__: **"High Availability Fault Tolerant Architectures Implemented into FPGAs"**, Straka, M.; Kotasek, Z.;, Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on , vol., no., pp.108-115, 27-29 Aug. 2009//
    * //__Citation__: **"Checker Design for On-line Testing of Xilinx FPGA Communication Protocols"**, Straka, M.; Tobola, J.; Kotasek, Z.;, Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on , vol., no., pp.152-160, 26-28 Sept. 2007//
    * //__Citation__: **"One-to-Many: Context-Oriented Code for Concurrent Error Detection"**, Osnat Keren, Journal of Electronic Testing. 26, 3 (June 2010), 337-353.//
    * //__Citation__: **"Duplication Based One-to-Many Coding for Trojan HW Detection"**, Keren, O.; Levin, I.; Karpovsky, M.;, Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on , vol., no., pp.160-166, 6-8 Oct. 2010//
    * //__Citation__: **"Online Protocol Testing for FPGA Based Fault Tolerant Systems"**, Tobola, J.; Kotasek, Z.; Korenek, J.; Martinek, T.; Straka, M.;, Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on , vol., no., pp.676-679, 29-31 Aug. 2007//
    * //__Citation__: **"The Design of On-line Checkers and Their Use in Verification and Testing"**, Kotásek Zdeněk, Straka Martin, In: Acta Electrotechnica et Informatica, roč. 2009, č. 3, SK, s. 8-15, ISSN 1335-8243//
    * //__Citation__: **"Assertion based on-line fault detection applied on UHF RFID tag"**, Mezzah, I.;Kermia, O. ; Chemali, H. ; Abdelmalek, O. ; Beroulle, V. ; Hely, D.:, In: Design and Test Symposium (IDT), 2013 8th IEEE International Design and Test Symposium,vol., no., pp.1-5, 16-18 Dec. 2013 //
    * //__Citation__: **"Safety-Related Instrumentation and Control Systems and a Problem of the Hidden Faults"**, Drozd, M; Drozd, A, 2014 10TH INTERNATIONAL CONFERENCE ON DIGITAL TECHNOLOGIES (DT), pp. 64 - 67, 2014. ISBN 978-1-4799-3303-7.//


  * **Dependable Design for FPGA based on Duplex System and Reconfiguration** (Stať ve sborníku) 2006, KUBALÍK P., DOBIÁŠ R., KUBÁTOVÁ H. In Proceedings of 9th Euromicro Conference on Digital System Design, DSD2006. Los Alamitos: IEEE Computer Society, 2006, p. 139-145. ISBN 0-7695-2609-8. {{:publication:dsd2006.pdf|pdf}}
    * //__Citation__: **"Contract Specification for Hardware Interoperability Testing and Fault Analysis"**, Silva, R.S.F.; Hesser, J.; Männer, R.;, Reliability, IEEE Transactions on , vol.60, no.1, pp.351-362, March 2011// 
    * //__Citation__: **"High Availability Fault Tolerant Architectures Implemented into FPGAs"**, Straka, M.; Kotasek, Z.;, Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on Digital System Design, vol., no., pp.108-115, 27-29 Aug. 2009.//
    * //__Citation__: **"Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA"**, Kastil, J.;Straka, M.;Miculka, L.; Kotasek, Z.;, Digital System Design 2012. DSD '12. 15th Euromicro Conference on Digital System Design, vol., no., pp.250-257, 5-8 Sept. 2012.// 
    * //__Citation__: **"Fault tolerant system design and SEU injection based testing"**, Martin Straka, Jan Kastil, Zdenek Kotasek, Lukas Miculka, Microprocessors and Microsystems, Volume 37, Issue 2, March 2013, Pages 155-173, ISSN 0141-9331//

  * **Dependability Computation for Fault Tolerant Reconfigurable Duplex System** (Stať ve sborníku) 2006, KUBALÍK P., DOBIÁŠ R., KUBÁTOVÁ H. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS2006. Praha: CTU Publishing House, 2006, vol. 1, p. 100-102. ISBN 1-4244-0184-4. {{:publication:ddecs2006.pdf|pdf}}
    * //__Citation__: **"Reliability Optimization of Reconfigurable FPGA Based on Second-Order Approximation Domain-Partition"**, Mi Zhou, Lihong Shang, and Yu Hu, In Proceedings of the 2009 International Conference on Embedded Software and Systems (ICESS '09). IEEE Computer Society, Washington, DC, USA, 511-516//
    * //__Citation__: **"Reliability Optimization of Reconfigurable Computing-Based Fault-Tolerant System"**, Mi Zhou, Lihong Shang, Yu Hu, High Performance Computing and Communications, pp. 369-375, 11th IEEE International Conference on High Performance Computing and Communications, 2009//
    * //__Citation__: **"A fault-tolerant system-on-programmable-chip based on domain-partition and blind reconfiguration"**, Shang, Lihong; Zhou, Mi; Hu, Yu;  Adaptive Hardware and Systems (AHS), 2010 NASA/ESA Conference on , vol., no., pp.297-303, 15-18 June 2010//
    * //__Citation__: **"High Availability Fault Tolerant Architectures Implemented into FPGAs"**, Straka, M.; Kotasek, Z.; Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on , vol., no., pp.108-115, 27-29 Aug. 2009.//
    * //__Citation__: **"Service Availability Driven Re-configurable Embedded System Design"**, Anil Kumar and Shampa Chakarverty:, ICISTM 2011, CCIS 141, pp. 265–276, 2011, Springer-Verlag Berlin Heidelberg 2011//
    * //__Citation__: **"Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA"**, Kastil, J.; Straka, M.; Miculka, L.; Kotasek, Z., Digital System Design (DSD), 2012 15th Euromicro Conference on , vol., no., pp.250,257, 5-8 Sept. 2012//

  * **Design Methodology for High Reliable System** (Stať ve sborníku) 2006, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the Seventh International Scientific Conference on Electronic Computers and Informatics ECI 2006. Košice: Technická univerzita v Košiciach, 2006, vol. 1, p. 274-279. ISBN 80-8073-598-0. {{:publication:eci2006.pdf|pdf}}
  * **Output Grouping Method Based on a Similarity of Boolean Functions** (Stať ve sborníku) 2006, FIŠER P., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 7th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2006, p. 107-113. ISBN 3-86012-287-8. {{:publication:iwsbp06.pdf|pdf}}
  * **Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems** (Elektronický sborník (na CD-ROM nebo na webu)) 2006, SONZA REORDA M. S. R., STRAUBE B. S., KOTÁSEK Z. K., UBAR R. U., NOVÁK O., KUBÁTOVÁ H., KUBALÍK P., BUČEK J. Praha: Czech Technical University in Prague, 2006. 305 p. ISBN 1-4244-0185-2.
==== 2005 ====

  * **Design of Self-Testing Circuits Using Parity Codes** (Paper in Electronic Proceedings (CD-ROM or web)) 2005, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of Workshop 2005 [CD-ROM]. Prague: CTU, 2005, p. 214-215. ISBN 80-01-03201-9. (in Czech). 
  * **Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs** (Paper in Conference Proceedings) 2005, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the Work in Progress Session. Linz: Johannes Kepler University, 2005, p. 13-14. ISBN 3-902457-09-0. {{:publication:euromicro2005.pdf|pdf}}
  * **Highly Reliable Design Based on TSC Circuits** (Paper in Conference Proceedings) 2005, KUBALÍK P., KUBÁTOVÁ H. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 101-106. ISBN 80-01-03298-1. {{:publication:pad2005.pdf|pdf}}
  * **Dependability Computations for Fault-Tolerant System Based on FPGA** (Paper in Conference Proceedings) 2005, DOBIÁŠ R., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 12th International Conferrence on Electronics, Circuits and Systems. Monterey: IEEE Circuits and Systems Society, 2005, vol. 1, p. 377-380. ISBN 9973-61-100-4. {{:publication:icecs2005.pdf|pdf}}
    * //__Citation__: **"Reconfigurable Fault Tolerance: A Comprehensive Framework for Reliable and Adaptive FPGA-Based Space Computing"**, Adam Jacobs, Grzegorz Cieslewski, Alan D. George, Ann Gordon-Ross, and Herman Lam., ACM Trans. Reconfigurable Technol. Syst. 5, 4, Article 21 (December 2012), 30 pages. //


  * **Fault Classification for Self-checking Circuits Implemented in FPGA** (Paper in Conference Proceedings) 2005, KAFKA L., KUBALÍK P., KUBÁTOVÁ H., NOVÁK O. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p.  228-231. ISBN 963 9364 48 7. {{:publication:ddecs2005.pdf|pdf}}
  * **Parity Codes Used for On-line Testing in FPGA** (Článek) 2005, KUBALÍK P., KUBÁTOVÁ H. Acta Polytechnica. 2005, vol. 45, no. 6, p. 53-59. ISSN 1210-2709. {{:publication:ap2005.pdf|pdf}}
==== 2004 ====

  * **Postgraduate Study Report 2004** KUBALÍK P., KUBÁTOVÁ H. Prague: CTU, Faculty of Electrical Engineering, 2004. {{:publication:minimal2004.pdf|pdf}}
  * **Fault Tolerant Design Methodology** (Paper in Electronic Proceedings (CD-ROM or web)) 2004, KUBALÍK P. In POSTER 2004 [CD-ROM]. Praha: CVUT FEL Praha, 2004. 
  * **Minimization of the Hamming Code Generator in Self Checking Circuits** (Paper in Conference Proceedings) 2004, KUBALÍK P., FIŠER P., KUBÁTOVÁ H. In Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04. Zielona Gora: University of Zielona Gora, 2004, p. 161-166. ISBN 83-89712-15-6. {{:publication:desdes2004.pdf|pdf}}
  * **High Reliable FPGA Based System Design Methodology** (Paper in Conference Proceedings) 2004, KUBALÍK P., KUBÁTOVÁ H. In Work in Progress Session of 30th EUROMICRO and DSD 2004. Linz: Universität Linz, 2004, p. 30-31. ISBN 3-902457-05-8. {{:publication:euromicro2004.pdf|pdf}}
  * **On-line Testing for FPGA** (Paper in Conference Proceedings) 2004, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 194-199. ISBN 80-8073-150-0. {{:publication:eci2004.pdf|pdf}}

==== 2003 ====

   * **FPGA Implementation of USB 1.1 Device Core** (Paper in Conference Proceedings) 2003, KUBALÍK P., BUČEK J. In Poster 2003. Prague: CTU, Faculty of Electrical Engineering, 2003, p. IC22.{{:publication:poster2003.pdf|pdf}}
   * **FPGA Implementation of USB 1.1 Device Core** (Paper in Electronic Proceedings (CD-ROM or web)) 2003, KUBALÍK P., BUČEK J. In Proceedings of Workshop 2003 (online) [CD-ROM]. Prague: CTU, 2003, vol. A, p. 304-305. ISBN 80-01-02708-2. 
   * **Design of Self Checking Circuits Based on FPGA** (Paper in Conference Proceedings) 2003, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 15th International Conference on Microelectronics. Cairo: Cairo University, 2003, p. 378-381. ISBN 977-05-2010-1. {{:publication:icm2003.pdf|pdf}}
     *  //__Citation__: **"Design Space Exploration for the Design of Reliable SRAM-Based FPGA Systems"**, Cristiana Bolchini and Antonio Miele, In Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT '08). IEEE Computer Society, Washington, DC, USA, 332-340. 2008.//
     *  //__Citation__: **"Applying partial fault tolerance with explicit area constraints"**, David L. Foster; Darrin M. Hanna, International Journal of Embedded Systems (IJES), Vol. 5, No. 1/2, 2013//
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