publication:public_list
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publication:public_list [2017/01/20 13:11] xkubalik [2011] |
publication:public_list [2017/01/20 13:50] xkubalik [2009] |
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| * //__Citation__: **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// | * //__Citation__: **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// | ||
| * //__Citation__: **"Safety Automata Network for Interlocking System"**, Trifonov, V.,: Mechanics Transport Communications, Academic journal, 2011.// | * //__Citation__: **"Safety Automata Network for Interlocking System"**, Trifonov, V.,: Mechanics Transport Communications, Academic journal, 2011.// | ||
| - | + | * //__Citation__: **"Modern methods in railway interlocking algorithms design"**, Piotr Kawaleca, Marcin Rżysko, Microprocessors and Microsystems, 2015. ISSN 0141-9331.// | |
| + | * //__Citation__: **"Algorithms and hardware description languages in railway interlocking logic design"**, Piotr Kawalec, Marcin Rżysko, 13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems — PDES 2015, vol. 48, no. 4, pp. 498 - 503, 2015.// | ||
| ==== 2008 ==== | ==== 2008 ==== | ||
publication/public_list.txt · Last modified: 2017/10/10 12:14 by xkubalik
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