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====== All publications ====== | ====== All publications ====== | ||
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+ | ==== 2016 ==== | ||
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+ | Buček, J.; Kubalík, P.; Lórencz, R.; Zahradnický, T. | ||
+ | Design of a Residue Number System Based Linear System Solver in Hardware | ||
+ | Journal of Signal Processing Systems. 2016, 1-14. ISSN 1939-8018. | ||
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+ | Bartík, M.; Ubik, S.; Kubalík, P. | ||
+ | A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time | ||
+ | In: ReConFig’16. Piscataway: IEEE, 2016, ISBN 978-1-5090-3706-3. | ||
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+ | Bartík, M.; Ubik, S.; Kubalík, P. | ||
+ | Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase | ||
+ | In: Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016, pp. 89-92. ISBN 978-80-214-5376-0. | ||
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==== 2015 ==== | ==== 2015 ==== |