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====== All publications ====== | ====== All publications ====== | ||
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+ | ==== 2016 ==== | ||
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+ | * **Design of a Residue Number System Based Linear System Solver in Hardware**, Buček, J.; Kubalík, P.; Lórencz, R.; Zahradnický, T., Journal of Signal Processing Systems. 2016, 1-14. ISSN 1939-8018. | ||
+ | * **A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time**, Bartík, M.; Ubik, S.; Kubalík, P., In: ReConFig’16. Piscataway: IEEE, 2016, ISBN 978-1-5090-3706-3. | ||
+ | * **Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase**, Bartík, M.; Ubik, S.; Kubalík, P., In: Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016, pp. 89-92. ISBN 978-80-214-5376-0. | ||
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==== 2015 ==== | ==== 2015 ==== | ||
+ | * **LZ4 Compression Algorithm on FPGA**, Bartík, M., S. Ubik, and P. Kubalík, 21st IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, 2015-12-06/2015-12-09. New York: Institute of Electrical and Electronics Engineers, 2015, vol. 1, pp. 179-182. ISBN 978-1-4799-2451-6. | ||
+ | * **Rychlé bezztrátové kompresní algoritmy**, Bartík, M., S. Ubik, and P. Kubalík, Sborník příspěvků PAD 2015. Počítačové architektury a diagnostika 2015, Zlín, 2015-09-02/2015-09-04. Zlín: Universita Tomáše Bati ve Zlíně, 2015, pp. 31-36. ISBN 978-80-7454-522-1. | ||
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==== 2014 ==== | ==== 2014 ==== | ||
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* **Fault Models Usability Study for On-line Tested FPGA**, Borecký,J., Kohlík,M., Kubátová,H., Kubalík, P., Proceedings of the 13th Euromicro Conference on Digital System Design, Oulu, 2011, pp.(287-290) {{:publication:dsd2011.pdf|pdf}} | * **Fault Models Usability Study for On-line Tested FPGA**, Borecký,J., Kohlík,M., Kubátová,H., Kubalík, P., Proceedings of the 13th Euromicro Conference on Digital System Design, Oulu, 2011, pp.(287-290) {{:publication:dsd2011.pdf|pdf}} | ||
* //__Citation__: **"A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip"**, Cédric Killian, Camel Tanougast, Fabrice Monteiro, and Abbas Dandache, Journal of Electrical and Computer Engineering, vol. 2012, Article ID 843239, 16 pages, 2012. doi:10.1155/2012/843239.// | * //__Citation__: **"A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip"**, Cédric Killian, Camel Tanougast, Fabrice Monteiro, and Abbas Dandache, Journal of Electrical and Computer Engineering, vol. 2012, Article ID 843239, 16 pages, 2012. doi:10.1155/2012/843239.// | ||
+ | * //__Citation__: **"Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip"**, Eghbal, A.; Yaghini, P.M.; Bagherzadeh, N.; Khayambashi, M., Computers, IEEE Transactions on, vol. 64, pp. 3591 - 3604, 2015.// | ||
+ | * //__Citation__: **"DAO: Dual module redundancy with AND/OR logic voter for FPGA hardening"**, Meisong Zheng; Zilong Wang; Lijian Li, Reliability Systems Engineering (ICRSE), 2015 First International Conference on, pp. 1 - 5, 2015.// | ||
==== 2010 ==== | ==== 2010 ==== | ||
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* //__Citation__: **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// | * //__Citation__: **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// | ||
* //__Citation__: **"Safety Automata Network for Interlocking System"**, Trifonov, V.,: Mechanics Transport Communications, Academic journal, 2011.// | * //__Citation__: **"Safety Automata Network for Interlocking System"**, Trifonov, V.,: Mechanics Transport Communications, Academic journal, 2011.// | ||
- | + | * //__Citation__: **"Modern methods in railway interlocking algorithms design"**, Piotr Kawaleca, Marcin Rżysko, Microprocessors and Microsystems, 2015. ISSN 0141-9331.// | |
+ | * //__Citation__: **"Algorithms and hardware description languages in railway interlocking logic design"**, Piotr Kawalec, Marcin Rżysko, 13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems — PDES 2015, vol. 48, no. 4, pp. 498 - 503, 2015.// | ||
==== 2008 ==== | ==== 2008 ==== | ||
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* //__Citation__: **"Soft core based embedded systems in critical aerospace applications"**, Sergio Cuenca-Asensia, Antonio Martínez-Álvareza, Felipe Restrepo-Callea, Francisco R. Palomob, Hipólito Guzmán-Mirandab, Miguel A. Aguirreb;, Journal of Systems Architecture, vol.57, issue 10, no.0, pp.886-895, November 2011// | * //__Citation__: **"Soft core based embedded systems in critical aerospace applications"**, Sergio Cuenca-Asensia, Antonio Martínez-Álvareza, Felipe Restrepo-Callea, Francisco R. Palomob, Hipólito Guzmán-Mirandab, Miguel A. Aguirreb;, Journal of Systems Architecture, vol.57, issue 10, no.0, pp.886-895, November 2011// | ||
* //__Citation__: **"Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms"**, Cristiana Bolchini, Antonio Miele, Chiara Sandionigi;, Journal of Electronic Testing, vol.29, issue 6, no., pp.779-793, December 2013// | * //__Citation__: **"Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms"**, Cristiana Bolchini, Antonio Miele, Chiara Sandionigi;, Journal of Electronic Testing, vol.29, issue 6, no., pp.779-793, December 2013// | ||
+ | * //__Citation__: **"Soft Error Mitigation in Soft-Core Processors"**, A Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle, FPGAs and Parallel Architectures for Aerospace Applications, vol. Chapter 16, 2016. ISBN 9783319143521.// | ||
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* //__Citation__: **"The Design of On-line Checkers and Their Use in Verification and Testing"**, Kotásek Zdeněk, Straka Martin, In: Acta Electrotechnica et Informatica, roč. 2009, č. 3, SK, s. 8-15, ISSN 1335-8243// | * //__Citation__: **"The Design of On-line Checkers and Their Use in Verification and Testing"**, Kotásek Zdeněk, Straka Martin, In: Acta Electrotechnica et Informatica, roč. 2009, č. 3, SK, s. 8-15, ISSN 1335-8243// | ||
* //__Citation__: **"Assertion based on-line fault detection applied on UHF RFID tag"**, Mezzah, I.;Kermia, O. ; Chemali, H. ; Abdelmalek, O. ; Beroulle, V. ; Hely, D.:, In: Design and Test Symposium (IDT), 2013 8th IEEE International Design and Test Symposium,vol., no., pp.1-5, 16-18 Dec. 2013 // | * //__Citation__: **"Assertion based on-line fault detection applied on UHF RFID tag"**, Mezzah, I.;Kermia, O. ; Chemali, H. ; Abdelmalek, O. ; Beroulle, V. ; Hely, D.:, In: Design and Test Symposium (IDT), 2013 8th IEEE International Design and Test Symposium,vol., no., pp.1-5, 16-18 Dec. 2013 // | ||
+ | * //__Citation__: **"Safety-Related Instrumentation and Control Systems and a Problem of the Hidden Faults"**, Drozd, M; Drozd, A, 2014 10TH INTERNATIONAL CONFERENCE ON DIGITAL TECHNOLOGIES (DT), pp. 64 - 67, 2014. ISBN 978-1-4799-3303-7.// | ||