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* **Dependable design technique for system-on-chip** (Článek) 2008, KUBALÍK P., KUBÁTOVÁ H. Journal of Systems Architecture. 2008, vol. 2008, no. 54, p. 452-464. ISSN 1383-7621. | * **Dependable design technique for system-on-chip** (Článek) 2008, KUBALÍK P., KUBÁTOVÁ H. Journal of Systems Architecture. 2008, vol. 2008, no. 54, p. 452-464. ISSN 1383-7621. | ||
- | * //__Citation__: Sergio Cuenca-Asensia, Antonio Martínez-Álvareza, Felipe Restrepo-Callea, Francisco R. Palomob, Hipólito Guzmán-Mirandab, Miguel A. Aguirreb; "Soft core based embedded systems in critical aerospace applications" Journal of Systems Architecture, vol.57, issue 10, no.0, pp.886-895, November 2011// | + | * //__Citation__: **"Soft core based embedded systems in critical aerospace applications"**, Sergio Cuenca-Asensia, Antonio Martínez-Álvareza, Felipe Restrepo-Callea, Francisco R. Palomob, Hipólito Guzmán-Mirandab, Miguel A. Aguirreb;, Journal of Systems Architecture, vol.57, issue 10, no.0, pp.886-895, November 2011// |
- | * //__Citation__: Cristiana Bolchini, Antonio Miele, Chiara Sandionigi; "Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms" Journal of Electronic Testing, vol.29, issue 6, no., pp.779-793, December 2013// | + | * //__Citation__: **"Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms"**, Cristiana Bolchini, Antonio Miele, Chiara Sandionigi;, Journal of Electronic Testing, vol.29, issue 6, no., pp.779-793, December 2013// |
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* **Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System** (Stať ve sborníku) 2007, KUBALÍK P., KVASNIČKA J., KUBÁTOVÁ H. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 357-360. ISBN 1-4244-1161-0. {{:publication:ddecs2007.pdf|pdf}} | * **Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System** (Stať ve sborníku) 2007, KUBALÍK P., KVASNIČKA J., KUBÁTOVÁ H. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 357-360. ISBN 1-4244-1161-0. {{:publication:ddecs2007.pdf|pdf}} | ||
- | * //__Citation__: "Speeding up Fault Simulation using Parallel Fault Simulation", Jiahua Fan and Zhifeng Zhang;, Procedia Engineering, Elsevier, vol.15, no.0, pp.1817-1821, CEIS 2011// | + | * //__Citation__: **"Speeding up Fault Simulation using Parallel Fault Simulation"**, Jiahua Fan and Zhifeng Zhang;, Procedia Engineering, Elsevier, vol.15, no.0, pp.1817-1821, CEIS 2011// |
* **An FPGA based fault emulator** (Stať ve sborníku) 2007, KVASNIČKA J., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007. Linz: Johannes Kepler University, 2007, p. 42-43. ISBN 978-3-902457-16-5. {{:publication:dsd2007.pdf|pdf}} | * **An FPGA based fault emulator** (Stať ve sborníku) 2007, KVASNIČKA J., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007. Linz: Johannes Kepler University, 2007, p. 42-43. ISBN 978-3-902457-16-5. {{:publication:dsd2007.pdf|pdf}} |