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====== All publications ====== | ====== All publications ====== | ||
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+ | ==== 2015 ==== | ||
+ | |||
+ | ==== 2014 ==== | ||
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+ | * **An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries**,Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R., Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems. 21st IEEE International Conference on Electronics Circuits and Systems, Marseille, 2014-12-07/2014-12-10. Monterey: IEEE Circuits and Systems Society, 2014, pp. 706-709. ISBN 978-1-4799-4242-8. | ||
==== 2013 ==== | ==== 2013 ==== | ||
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* **Fault-tolerant and fail-safe design based on reconfiguration**, Kubátová,H., Kubalík, P., Chapter in book: Design and Test Technology for Dependable Systems-on-Chip, 2011, pp.(175-194) | * **Fault-tolerant and fail-safe design based on reconfiguration**, Kubátová,H., Kubalík, P., Chapter in book: Design and Test Technology for Dependable Systems-on-Chip, 2011, pp.(175-194) | ||
* **Fault Models Usability Study for On-line Tested FPGA**, Borecký,J., Kohlík,M., Kubátová,H., Kubalík, P., Proceedings of the 13th Euromicro Conference on Digital System Design, Oulu, 2011, pp.(287-290) {{:publication:dsd2011.pdf|pdf}} | * **Fault Models Usability Study for On-line Tested FPGA**, Borecký,J., Kohlík,M., Kubátová,H., Kubalík, P., Proceedings of the 13th Euromicro Conference on Digital System Design, Oulu, 2011, pp.(287-290) {{:publication:dsd2011.pdf|pdf}} | ||
+ | * //__Citation__: **"A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip"**, Cédric Killian, Camel Tanougast, Fabrice Monteiro, and Abbas Dandache, Journal of Electrical and Computer Engineering, vol. 2012, Article ID 843239, 16 pages, 2012. doi:10.1155/2012/843239.// | ||
==== 2010 ==== | ==== 2010 ==== | ||
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* **Reliable Railway Station System based on Regular Structure implemented in FPGA**, Borecký,J., Kubalík,P., Kubátová,H, Proc. of 12th EUROMICRO Conference on Digital System Design, Patras, 2009, pp.(348-354). {{:publication:dsd2009.pdf|pdf}} | * **Reliable Railway Station System based on Regular Structure implemented in FPGA**, Borecký,J., Kubalík,P., Kubátová,H, Proc. of 12th EUROMICRO Conference on Digital System Design, Patras, 2009, pp.(348-354). {{:publication:dsd2009.pdf|pdf}} | ||
- | * //__Citation__: Cinzia Bernardeschi, Luca Cassano, Andrea Domenici,Giancarlo Gennaro, Mario Pasquariello; **"Simulated Injection of Radiation-Induced Logic Faults in FPGAs"** , The Third International Conference on Advances in System Testing and Validation Lifecycle, pp.84-89, VALID 2011// | + | * //__Citation__: **"Simulated Injection of Radiation-Induced Logic Faults in FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici,Giancarlo Gennaro, Mario Pasquariello;, The Third International Conference on Advances in System Testing and Validation Lifecycle, pp.84-89, VALID 2011// |
- | * //__Citation__: Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// | + | * //__Citation__: **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// |
- | * //__Citation__: Trifonov, V.,: **"Safety Automata Network for Interlocking System"**, Mechanics Transport Communications, Academic journal, 2011.// | + | * //__Citation__: **"Safety Automata Network for Interlocking System"**, Trifonov, V.,: Mechanics Transport Communications, Academic journal, 2011.// |
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* **Dependable design technique for system-on-chip** (Článek) 2008, KUBALÍK P., KUBÁTOVÁ H. Journal of Systems Architecture. 2008, vol. 2008, no. 54, p. 452-464. ISSN 1383-7621. | * **Dependable design technique for system-on-chip** (Článek) 2008, KUBALÍK P., KUBÁTOVÁ H. Journal of Systems Architecture. 2008, vol. 2008, no. 54, p. 452-464. ISSN 1383-7621. | ||
- | * //__Citation__: Sergio Cuenca-Asensia, Antonio Martínez-Álvareza, Felipe Restrepo-Callea, Francisco R. Palomob, Hipólito Guzmán-Mirandab, Miguel A. Aguirreb; "Soft core based embedded systems in critical aerospace applications" Journal of Systems Architecture, vol.57, issue 10, no.0, pp.886-895, November 2011// | + | * //__Citation__: **"Soft core based embedded systems in critical aerospace applications"**, Sergio Cuenca-Asensia, Antonio Martínez-Álvareza, Felipe Restrepo-Callea, Francisco R. Palomob, Hipólito Guzmán-Mirandab, Miguel A. Aguirreb;, Journal of Systems Architecture, vol.57, issue 10, no.0, pp.886-895, November 2011// |
- | * //__Citation__: Cristiana Bolchini, Antonio Miele, Chiara Sandionigi; "Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms" Journal of Electronic Testing, vol.29, issue 6, no., pp.779-793, December 2013// | + | * //__Citation__: **"Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms"**, Cristiana Bolchini, Antonio Miele, Chiara Sandionigi;, Journal of Electronic Testing, vol.29, issue 6, no., pp.779-793, December 2013// |
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* **Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System** (Stať ve sborníku) 2007, KUBALÍK P., KVASNIČKA J., KUBÁTOVÁ H. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 357-360. ISBN 1-4244-1161-0. {{:publication:ddecs2007.pdf|pdf}} | * **Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System** (Stať ve sborníku) 2007, KUBALÍK P., KVASNIČKA J., KUBÁTOVÁ H. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 357-360. ISBN 1-4244-1161-0. {{:publication:ddecs2007.pdf|pdf}} | ||
- | * //__Citation__: Jiahua Fan and Zhifeng Zhang; , "Speeding up Fault Simulation using Parallel Fault Simulation" Procedia Engineering, Elsevier, vol.15, no.0, pp.1817-1821, CEIS 2011// | + | * //__Citation__: **"Speeding up Fault Simulation using Parallel Fault Simulation"**, Jiahua Fan and Zhifeng Zhang;, Procedia Engineering, Elsevier, vol.15, no.0, pp.1817-1821, CEIS 2011// |
* **An FPGA based fault emulator** (Stať ve sborníku) 2007, KVASNIČKA J., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007. Linz: Johannes Kepler University, 2007, p. 42-43. ISBN 978-3-902457-16-5. {{:publication:dsd2007.pdf|pdf}} | * **An FPGA based fault emulator** (Stať ve sborníku) 2007, KVASNIČKA J., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007. Linz: Johannes Kepler University, 2007, p. 42-43. ISBN 978-3-902457-16-5. {{:publication:dsd2007.pdf|pdf}} |