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publication:public_list [2014/02/28 14:47] xkubalik [2008] |
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* **Reliable Railway Station System based on Regular Structure implemented in FPGA**, Borecký,J., Kubalík,P., Kubátová,H, Proc. of 12th EUROMICRO Conference on Digital System Design, Patras, 2009, pp.(348-354). {{:publication:dsd2009.pdf|pdf}} | * **Reliable Railway Station System based on Regular Structure implemented in FPGA**, Borecký,J., Kubalík,P., Kubátová,H, Proc. of 12th EUROMICRO Conference on Digital System Design, Patras, 2009, pp.(348-354). {{:publication:dsd2009.pdf|pdf}} | ||
* //__Citation__: Cinzia Bernardeschi, Luca Cassano, Andrea Domenici,Giancarlo Gennaro, Mario Pasquariello; "Simulated Injection of Radiation-Induced Logic Faults in FPGAs" , The Third International Conference on Advances in System Testing and Validation Lifecycle, pp.84-89, VALID 2011// | * //__Citation__: Cinzia Bernardeschi, Luca Cassano, Andrea Domenici,Giancarlo Gennaro, Mario Pasquariello; "Simulated Injection of Radiation-Induced Logic Faults in FPGAs" , The Third International Conference on Advances in System Testing and Validation Lifecycle, pp.84-89, VALID 2011// | ||
+ | * //__Citation__: Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// | ||
==== 2008 ==== | ==== 2008 ==== | ||
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* **Highly Reliable Design Based on TSC Circuits** (Paper in Conference Proceedings) 2005, KUBALÍK P., KUBÁTOVÁ H. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 101-106. ISBN 80-01-03298-1. {{:publication:pad2005.pdf|pdf}} | * **Highly Reliable Design Based on TSC Circuits** (Paper in Conference Proceedings) 2005, KUBALÍK P., KUBÁTOVÁ H. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 101-106. ISBN 80-01-03298-1. {{:publication:pad2005.pdf|pdf}} | ||
* **Dependability Computations for Fault-Tolerant System Based on FPGA** (Paper in Conference Proceedings) 2005, DOBIÁŠ R., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 12th International Conferrence on Electronics, Circuits and Systems. Monterey: IEEE Circuits and Systems Society, 2005, vol. 1, p. 377-380. ISBN 9973-61-100-4. {{:publication:icecs2005.pdf|pdf}} | * **Dependability Computations for Fault-Tolerant System Based on FPGA** (Paper in Conference Proceedings) 2005, DOBIÁŠ R., KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 12th International Conferrence on Electronics, Circuits and Systems. Monterey: IEEE Circuits and Systems Society, 2005, vol. 1, p. 377-380. ISBN 9973-61-100-4. {{:publication:icecs2005.pdf|pdf}} | ||
+ | * //__Citation__: Adam Jacobs, Grzegorz Cieslewski, Alan D. George, Ann Gordon-Ross, and Herman Lam. 2012. Reconfigurable Fault Tolerance: A Comprehensive Framework for Reliable and Adaptive FPGA-Based Space Computing. ACM Trans. Reconfigurable Technol. Syst. 5, 4, Article 21 (December 2012), 30 pages. // | ||
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* **Fault Classification for Self-checking Circuits Implemented in FPGA** (Paper in Conference Proceedings) 2005, KAFKA L., KUBALÍK P., KUBÁTOVÁ H., NOVÁK O. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p. 228-231. ISBN 963 9364 48 7. {{:publication:ddecs2005.pdf|pdf}} | * **Fault Classification for Self-checking Circuits Implemented in FPGA** (Paper in Conference Proceedings) 2005, KAFKA L., KUBALÍK P., KUBÁTOVÁ H., NOVÁK O. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p. 228-231. ISBN 963 9364 48 7. {{:publication:ddecs2005.pdf|pdf}} | ||
* **Parity Codes Used for On-line Testing in FPGA** (Článek) 2005, KUBALÍK P., KUBÁTOVÁ H. Acta Polytechnica. 2005, vol. 45, no. 6, p. 53-59. ISSN 1210-2709. {{:publication:ap2005.pdf|pdf}} | * **Parity Codes Used for On-line Testing in FPGA** (Článek) 2005, KUBALÍK P., KUBÁTOVÁ H. Acta Polytechnica. 2005, vol. 45, no. 6, p. 53-59. ISSN 1210-2709. {{:publication:ap2005.pdf|pdf}} | ||
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==== 2004 ==== | ==== 2004 ==== | ||