# --------------------------------------------------------------
# indices of commands in following two lists must correspond !!!
# --------------------------------------------------------------


# list of commands to be displayed in command window

set abcCmdList {
"Any Command              TCL"
"--- Basic ------------------"
"alias"
"echo"
"empty"
"help"
"history"
"ls"
"recall"
"quit"
"set"
"source"
"time                     TCL"
"unalias"
"undo"
"unset"
"--- Input ------------------"
"read                     TCL"
"read_aiger"
"read_baf"
"read_bench"
"read_blif"
"read_blif_mv"
"read_dsd"
"read_eqn"
"read_pla"
"read_truth"
"read_verilog"
"--- Output -----------------"
"write"
"write_aiger"
"write_baf"
"write_bench"
"write_blif"
"write_blif_mv"
"write_cnf"
"write_counter"
"write_dot"
"write_eqn"
"write_hie"
"write_gml"
"write_pla"
"write_verilog"
"--- Printing ---------------"
"print_auto               TCL"
"print_exdc"
"print_factor"
"print_fanio              TCL"
"print_gates              TCL"
"print_io"
"print_kmap"
"print_latch              TCL"
"print_level"
"print_mffc"
"print_sharing"
"print_stats              TCL"
"print_supp"
"print_symm               TCL"
"print_unate              TCL"
"show"
"show_cut"
"show_bdd"
"--- Synthesis --------------"
"-- Combinational synthesis -"
"balance"
"cleanup"
"collapse"
"dsd"
"fx"
"multi"
"refactor"
"renode"
"rewrite"
"rr"
"strash"
"sweep"
"-- Sequential synthesis ----"
"cycle"
"init"
"lcorr"
"retime"
"scleanup"
"ssw"
"undc"
"xsim"
"zero"
"--- Technology mapping -----"
"-- LUT-mapping -------------"
"if"
"ffpga"
"fpga"
"imfs"
"lutpack"
"print_lut"
"read_lut"
"-- Standard cell mapping ---"
"attach"
"map"
"print_library"
"read_library"
"read_super"
"super"
"unmap"
"--- Fraiging ---------------"
"fraig"
"fraig_trust"
"fraig_store"
"fraig_restore"
"fraig_clean"
"fraig_sweep"
"dress"
"--- Verification commands --"
"cec                      TCL"
"debug"
"dprove                   TCL"
"dsec                     TCL"
"iprove                   TCL"
"prove                    TCL"
"sat                      TCL"
"sec                      TCL"
"--- Unsorted ---------------"
"aig"
"append"
"bdd"
"cascade"
"capo"
"comb"
"cone"
"cut"
"demiter"
"double"
"espresso"
"exdc_free"
"exdc_get"
"exdc_set"
"ext_seq_dcs"
"frames"
"gen"
"logic"
"miter"
"muxes"
"mvsis"
"node"
"order"
"orpos"
"reorder"
"short_names"
"sis"
"sop"
"test"
}


# list of commands to be executed in output windows
set tclCmdList {
"abcAnyCommand {} outputData"
"--- Basic ---"
"abcAnyCommand {alias} outputData"
"abcAnyCommand {echo} outputData"
"abcAnyCommand {empty} outputData"
"abcAnyCommand {help} outputData"
"abcAnyCommand {history} outputData"
"abcAnyCommand {ls} outputData"
"abcAnyCommand {recall} outputData"
"abcAnyCommand {quit} outputData"
"abcAnyCommand {set} outputData"
"abcAnyCommand {source} outputData"
"abc_time outputData"
"abcAnyCommand {unalias} outputData"
"abcAnyCommand {undo} outputData"
"abcAnyCommand {unset} outputData"
"--- Input ---"
"abc_read outputData"
"abcAnyCommand {read_aiger} outputData"
"abcAnyCommand {read_baf} outputData"
"abcAnyCommand {read_bench} outputData"
"abcAnyCommand {read_blif} outputData"
"abcAnyCommand {read_blif_mv} outputData"
"abcAnyCommand {read_dsd} outputData"
"abcAnyCommand {read_eqn} outputData"
"abcAnyCommand {read_pla} outputData"
"abcAnyCommand {read_truth} outputData"
"abcAnyCommand {read_verilog} outputData"
"--- Output ---"
"abcAnyCommand {write} outputData"
"abcAnyCommand {write_aiger} outputData"
"abcAnyCommand {write_baf} outputData"
"abcAnyCommand {write_bench} outputData"
"abcAnyCommand {write_blif} outputData"
"abcAnyCommand {write_blif_mv} outputData"
"abcAnyCommand {write_cnf} outputData"
"abcAnyCommand {write_counter} outputData"
"abcAnyCommand {write_dot} outputData"
"abcAnyCommand {write_eqn} outputData"
"abcAnyCommand {write_hie} outputData"
"abcAnyCommand {write_gml} outputData"
"abcAnyCommand {write_pla} outputData"
"abcAnyCommand {write_verilog} outputData"
"--- Printing ---"
"abc_print_auto outputData"
"abcAnyCommand {print_exdc} outputData"
"abcAnyCommand {print_factor} outputData"
"abc_print_fanio outputData"
"abc_print_gates outputData"
"abcAnyCommand {print_io} outputData"
"abcAnyCommand {print_kmap} outputData"
"abc_print_latch outputData"
"abcAnyCommand {print_level} outputData"
"abcAnyCommand {print_mffc} outputData"
"abcAnyCommand {print_sharing} outputData"
"abc_print_stats outputData"
"abcAnyCommand {print_supp} outputData"
"abc_print_symm outputData"
"abc_print_unate outputData"
"abcAnyCommand {show} outputData"
"abcAnyCommand {show_cut} outputData"
"abcAnyCommand {show_bdd} outputData"
"--- Synthesis ---"
"-- Combinational synthesis --"
"abcAnyCommand {balance} outputData"
"abcAnyCommand {cleanup} outputData"
"abcAnyCommand {collapse} outputData"
"abcAnyCommand {dsd} outputData"
"abcAnyCommand {fx} outputData"
"abcAnyCommand {multi} outputData"
"abcAnyCommand {refactor} outputData"
"abcAnyCommand {renode} outputData"
"abcAnyCommand {rewrite} outputData"
"abcAnyCommand {rr} outputData"
"abcAnyCommand {strash} outputData"
"abcAnyCommand {sweep} outputData"
"-- Sequential synthesis --"
"abcAnyCommand {cycle} outputData"
"abcAnyCommand {init} outputData"
"abcAnyCommand {lcorr} outputData"
"abcAnyCommand {retime} outputData"
"abcAnyCommand {scleanup} outputData"
"abcAnyCommand {ssw} outputData"
"abcAnyCommand {undc} outputData"
"abcAnyCommand {xsim} outputData"
"abcAnyCommand {zero} outputData"
"--- Technology mapping ---"
"-- LUT-mapping --"
"abcAnyCommand {if} outputData"
"abcAnyCommand {ffpga} outputData"
"abcAnyCommand {fpga} outputData"
"abcAnyCommand {imfs} outputData"
"abcAnyCommand {lutpack} outputData"
"abcAnyCommand {print_lut} outputData"
"abcAnyCommand {read_lut} outputData"
"-- Standard cell mapping --"
"abcAnyCommand {attach} outputData"
"abcAnyCommand {map} outputData"
"abcAnyCommand {print_library} outputData"
"abcAnyCommand {read_library} outputData"
"abcAnyCommand {read_super} outputData"
"abcAnyCommand {super} outputData"
"abcAnyCommand {unmap} outputData"
"--- Fraiging ---"
"abcAnyCommand {fraig} outputData"
"abcAnyCommand {fraig_trust} outputData"
"abcAnyCommand {fraig_store} outputData"
"abcAnyCommand {fraig_restore} outputData"
"abcAnyCommand {fraig_clean} outputData"
"abcAnyCommand {fraig_sweep} outputData"
"abcAnyCommand {dress} outputData"
"--- Verification commands ---"
"abc_cec outputData"
"abcAnyCommand {debug} outputData"
"abc_dprove outputData"
"abc_dsec outputData"
"abc_iprove outputData"
"abc_prove outputData"
"abc_sat outputData"
"abc_sec outputData"
"--- Unsorted ---"
"abcAnyCommand {aig} outputData"
"abcAnyCommand {append} outputData"
"abcAnyCommand {bdd} outputData"
"abcAnyCommand {cascade} outputData"
"abcAnyCommand {capo} outputData"
"abcAnyCommand {comb} outputData"
"abcAnyCommand {cone} outputData"
"abcAnyCommand {cut} outputData"
"abcAnyCommand {demiter} outputData"
"abcAnyCommand {double} outputData"
"abcAnyCommand {espresso} outputData"
"abcAnyCommand {exdc_free} outputData"
"abcAnyCommand {exdc_get} outputData"
"abcAnyCommand {exdc_set} outputData"
"abcAnyCommand {ext_seq_dcs} outputData"
"abcAnyCommand {frames} outputData"
"abcAnyCommand {gen} outputData"
"abcAnyCommand {logic} outputData"
"abcAnyCommand {miter} outputData"
"abcAnyCommand {muxes} outputData"
"abcAnyCommand {mvsis} outputData"
"abcAnyCommand {node} outputData"
"abcAnyCommand {order} outputData"
"abcAnyCommand {orpos} outputData"
"abcAnyCommand {reorder} outputData"
"abcAnyCommand {short_names} outputData"
"abcAnyCommand {sis} outputData"
"abcAnyCommand {sop} outputData"
"abcAnyCommand {test} outputData"
}
