c_muller Project Status
Project File: | c_muller.ise | Current State: | Synthesized
Module Name: | cm |

- Errors:

No Errors
Target Device: | xa3s500e-4ftg256 |

- Warnings:

No Warnings
Product Version: | ISE 10.1 - WebPACK |

- Routing Results:

Design Goal: | Balanced |

- Timing Constraints:

Design Strategy: | Xilinx Default (unlocked) |

- Final Timing Score:

c_muller Partition Summary | [-]
No partition information was found.

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slices | 1 | 4656 | 0%
Number of 4 input LUTs | 1 | 9312 | 0%
Number of bonded IOBs | 3 | 190 | 1%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | čt 22. V 11:13:41 2008 | 0 | 0 | 0
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Date Generated: 06/10/2008 - 22:09:07