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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:44:45 05/10/2008 
-- Design Name: 
-- Module Name:    cm - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cm is
    Port ( S : in  STD_LOGIC;
           R : in  STD_LOGIC;
           out_c : out  STD_LOGIC);
end cm;

architecture Behavioral of cm is

	signal lev1a : std_logic;
	signal lev1c : std_logic;
	
	signal lev2a : std_logic;
	signal lev2b : std_logic;
	signal lev2c : std_logic;	
	
	signal lev3or : std_logic;		
	
	
begin





	lev2a <= lev1a and S;
	lev2b <= S and not R;
	lev2c <= not R and lev1c;
  
   lev3or <= lev2a or lev2b or lev2c;
	lev1a  <= lev3or;
	lev1c  <= lev3or;
	out_c <= lev3or;




end Behavioral;

