library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vme is
 Port ( indsr: in STD_LOGIC;
inldtack: in STD_LOGIC;
outlds: out STD_LOGIC;
outd: out STD_LOGIC; 
outcsc0 : out STD_LOGIC			--pridan pro simulaci
 );
 end vme;

architecture Behavioral of vme is 
component cm
Port ( S : in  STD_LOGIC;
R : in  STD_LOGIC;
out_c : out  STD_LOGIC);
end component;
signal dsr : STD_LOGIC;
signal ldtack : STD_LOGIC;
signal lds : STD_LOGIC;
signal d : STD_LOGIC;
signal csc0 : STD_LOGIC;
signal csc0S : STD_LOGIC;
signal csc0R : STD_LOGIC;
begin
dsr <= indsr;
ldtack <= inldtack;
outlds <= lds;
outd <= d;
lds<= csc0 ;
outcsc0 <= csc0;				--neni soucasti puvodniho VHDL, pro simulaci
d<= ldtack and csc0 ;
csc0CM : cm
port map ( csc0S , csc0R , csc0 );
csc0S <= dsr and (not ldtack) ;
csc0R <= (not dsr) ;

end Behavioral;