\select@language {czech}
\contentsline {chapter}{\numberline {}{Seznam obr\IeC {\'a}zk\IeC {\r u}}}{xv}{chapter*.5}
\contentsline {chapter}{\numberline {}{Seznam tabulek}}{xvii}{chapter*.6}
\contentsline {chapter}{\numberline {1}\IeC {\'U}vod}{1}{chapter.1}
\contentsline {section}{\numberline {1.1}Motivace}{1}{section.1.1}
\contentsline {section}{\numberline {1.2}Synchronn\IeC {\'\i } obvody a synchronizace}{1}{section.1.2}
\contentsline {section}{\numberline {1.3}Pro\IeC {\v c} m\IeC {\'a} smysl se zab\IeC {\'y}vat asynchronn\IeC {\'\i }mi obvody}{1}{section.1.3}
\contentsline {section}{\numberline {1.4}Hlavn\IeC {\'\i } nev\IeC {\'y}hody asynchronn\IeC {\'\i }ch obvod\IeC {\r u}}{1}{section.1.4}
\contentsline {section}{\numberline {1.5}P\IeC {\v r}\IeC {\'\i }nos }{2}{section.1.5}
\contentsline {chapter}{\numberline {2}Popis probl\IeC {\'e}mu, specifikace c\IeC {\'\i }le}{3}{chapter.2}
\contentsline {section}{\numberline {2.1}\IeC {\'U}vod do n\IeC {\'a}vrhov\IeC {\'y}ch vzor\IeC {\r u}}{3}{section.2.1}
\contentsline {section}{\numberline {2.2}Popis probl\IeC {\'e}mu}{3}{section.2.2}
\contentsline {section}{\numberline {2.3}Vyt\IeC {\'y}\IeC {\v c}en\IeC {\'\i } c\IeC {\'\i }l\IeC {\r u}}{3}{section.2.3}
\contentsline {subsection}{\numberline {2.3.1}Pojmov\IeC {\'e} c\IeC {\'\i }le}{3}{subsection.2.3.1}
\contentsline {subsection}{\numberline {2.3.2}Implementa\IeC {\v c}n\IeC {\'\i } c\IeC {\'\i }le}{4}{subsection.2.3.2}
\contentsline {subsection}{\numberline {2.3.3}Simula\IeC {\v c}n\IeC {\'\i } c\IeC {\'\i }l}{4}{subsection.2.3.3}
\contentsline {section}{\numberline {2.4}\IeC {\v C}\IeC {\'\i }m se zab\IeC {\'y}vat nebudu}{4}{section.2.4}
\contentsline {section}{\numberline {2.5}Existuj\IeC {\'\i }c\IeC {\'\i } n\IeC {\'a}stroje pro synt\IeC {\'e}zu asynchronn\IeC {\'\i }ch obvod\IeC {\r u}}{4}{section.2.5}
\contentsline {subsection}{\numberline {2.5.1}ATACS online}{4}{subsection.2.5.1}
\contentsline {subsection}{\numberline {2.5.2}Petrify}{5}{subsection.2.5.2}
\contentsline {chapter}{\numberline {3}Uveden\IeC {\'\i } do problematiky}{7}{chapter.3}
\contentsline {section}{\numberline {3.1}Speed Independent obvody}{7}{section.3.1}
\contentsline {subsection}{\numberline {3.1.1}Hazardy}{7}{subsection.3.1.1}
\contentsline {subsection}{\numberline {3.1.2}Modely zpo\IeC {\v z}d\IeC {\v e}n\IeC {\'\i } (Delay model)}{7}{subsection.3.1.2}
\contentsline {subsection}{\numberline {3.1.3} Vstupn\IeC {\v e}-v\IeC {\'y}stupn\IeC {\'\i } m\IeC {\'o}d (Input-Output mode)}{7}{subsection.3.1.3}
\contentsline {subsection}{\numberline {3.1.4}Synt\IeC {\'e}za Speed Independent obvodu}{8}{subsection.3.1.4}
\contentsline {subsection}{\numberline {3.1.5}Pro\IeC {\v c} jsem pou\IeC {\v z}il C-element}{8}{subsection.3.1.5}
\contentsline {subsection}{\numberline {3.1.6}Sign\IeC {\'a}lov\IeC {\v e} p\IeC {\v r}echodov\IeC {\'y} graf (Signal transition graph, STG)}{8}{subsection.3.1.6}
\contentsline {subsection}{\numberline {3.1.7}Stavov\IeC {\'y} graf (State Graph, SG)}{9}{subsection.3.1.7}
\contentsline {subsection}{\numberline {3.1.8}Regiony}{10}{subsection.3.1.8}
\contentsline {subsection}{\numberline {3.1.9} Excitovan\IeC {\'e} regiony(Excistation region, ER)}{10}{subsection.3.1.9}
\contentsline {subsection}{\numberline {3.1.10} Ust\IeC {\'a}len\IeC {\'e} regiony (Quiescent region, QR)}{10}{subsection.3.1.10}
\contentsline {subsection}{\numberline {3.1.11}Minimalizace}{10}{subsection.3.1.11}
\contentsline {subsection}{\numberline {3.1.12}\IeC {\v C}asov\IeC {\'y} diagram (Timing diagram)}{11}{subsection.3.1.12}
\contentsline {subsection}{\numberline {3.1.13}Vztah sign\IeC {\'a}lov\IeC {\v e} p\IeC {\v r}echodov\IeC {\'e}ho grafu a \IeC {\v c}asov\IeC {\'e}ho diagramu}{12}{subsection.3.1.13}
\contentsline {subsection}{\numberline {3.1.14}Matematick\IeC {\'e} vyj\IeC {\'a}d\IeC {\v r}en\IeC {\'\i } algoritmu pro transformaci STG na Stavov\IeC {\'y} Graf}{12}{subsection.3.1.14}
\contentsline {subsection}{\numberline {3.1.15}Muller C-element}{14}{subsection.3.1.15}
\contentsline {subsection}{\numberline {3.1.16}C-element ve VHDL }{16}{subsection.3.1.16}
\contentsline {section}{\numberline {3.2}Fundament\IeC {\'a}ln\IeC {\'\i } m\IeC {\'o}d}{17}{section.3.2}
\contentsline {subsection}{\numberline {3.2.1}Synt\IeC {\'e}za podle fundament\IeC {\'a}ln\IeC {\'\i }ho m\IeC {\'o}du}{18}{subsection.3.2.1}
\contentsline {subsection}{\numberline {3.2.2}Nev\IeC {\'y}hody oproti Vstupn\IeC {\v e}-v\IeC {\'y}stupn\IeC {\'\i }mu m\IeC {\'o}du}{18}{subsection.3.2.2}
\contentsline {section}{\numberline {3.3}P\IeC {\v r}\IeC {\'\i }klad postupu synt\IeC {\'e}zy }{18}{section.3.3}
\contentsline {chapter}{\numberline {4}Anal\IeC {\'y}za a n\IeC {\'a}vrh \IeC {\v r}e\IeC {\v s}en\IeC {\'\i }}{25}{chapter.4}
\contentsline {section}{\numberline {4.1}Shrnut\IeC {\'\i } p\IeC {\v r}ed anal\IeC {\'y}zou a n\IeC {\'a}vrhem}{25}{section.4.1}
\contentsline {section}{\numberline {4.2}Implementa\IeC {\v c}n\IeC {\'\i } jazyk}{25}{section.4.2}
\contentsline {section}{\numberline {4.3}Vstup programu}{25}{section.4.3}
\contentsline {section}{\numberline {4.4}Reprezentace grafu}{25}{section.4.4}
\contentsline {section}{\numberline {4.5}N\IeC {\'a}vrh reprezentace grafu}{25}{section.4.5}
\contentsline {section}{\numberline {4.6}Po\IeC {\v c}\IeC {\'a}te\IeC {\v c}n\IeC {\'\i } zak\IeC {\'o}dov\IeC {\'a}n\IeC {\'\i }}{26}{section.4.6}
\contentsline {section}{\numberline {4.7}N\IeC {\'a}vrh reprezentace po\IeC {\v c}\IeC {\'a}te\IeC {\v c}n\IeC {\'\i }ho zak\IeC {\'o}dov\IeC {\'a}n\IeC {\'\i }}{26}{section.4.7}
\contentsline {section}{\numberline {4.8}Vstupy, v\IeC {\'y}stupy a intern\IeC {\'\i } sign\IeC {\'a}ly}{26}{section.4.8}
\contentsline {section}{\numberline {4.9}N\IeC {\'a}vrh reprezentace vstup\IeC {\r u}, v\IeC {\'y}stup\IeC {\r u} a intern\IeC {\'\i }ch sign\IeC {\'a}l\IeC {\r u}}{26}{section.4.9}
\contentsline {section}{\numberline {4.10}Marking}{26}{section.4.10}
\contentsline {section}{\numberline {4.11}N\IeC {\'a}vrh p\IeC {\v r}id\IeC {\v e}lov\IeC {\'a}n\IeC {\'\i } token\IeC {\r u}}{26}{section.4.11}
\contentsline {section}{\numberline {4.12}Modul zpracov\IeC {\'a}n\IeC {\'\i } textu}{26}{section.4.12}
\contentsline {section}{\numberline {4.13}N\IeC {\'a}vrh modulu pro zpracov\IeC {\'a}n\IeC {\'\i } textu}{27}{section.4.13}
\contentsline {section}{\numberline {4.14}Modul pro zpracov\IeC {\'a}n\IeC {\'\i } p\IeC {\v r}\IeC {\'\i }kaz\IeC {\r u}}{27}{section.4.14}
\contentsline {section}{\numberline {4.15}N\IeC {\'a}vrh modulu pro zpracov\IeC {\'a}n\IeC {\'\i } p\IeC {\v r}\IeC {\'\i }kaz\IeC {\r u}}{27}{section.4.15}
\contentsline {section}{\numberline {4.16}Modul pro transformaci}{27}{section.4.16}
\contentsline {section}{\numberline {4.17}N\IeC {\'a}vrh modulu pro transformaci}{27}{section.4.17}
\contentsline {section}{\numberline {4.18}Modul pro vytvo\IeC {\v r}en\IeC {\'\i } region\IeC {\r u}}{28}{section.4.18}
\contentsline {section}{\numberline {4.19}N\IeC {\'a}vrh modulu pro vytv\IeC {\'a}\IeC {\v r}en\IeC {\'\i } region\IeC {\r u}}{28}{section.4.19}
\contentsline {section}{\numberline {4.20}Modul pro minimalizaci}{28}{section.4.20}
\contentsline {section}{\numberline {4.21}D\IeC {\r u}vody pou\IeC {\v z}it\IeC {\'\i } vlastn\IeC {\'\i }ho minimaliza\IeC {\v c}n\IeC {\'\i }ho algoritmu}{29}{section.4.21}
\contentsline {section}{\numberline {4.22}Algoritmus minimalizace}{29}{section.4.22}
\contentsline {section}{\numberline {4.23}N\IeC {\'a}vrh pro modul minimalizace}{29}{section.4.23}
\contentsline {section}{\numberline {4.24}N\IeC {\'a}vrh algoritmu}{30}{section.4.24}
\contentsline {section}{\numberline {4.25}V\IeC {\'y}stup programu}{30}{section.4.25}
\contentsline {section}{\numberline {4.26}N\IeC {\'a}vrh v\IeC {\'y}stupu programu}{30}{section.4.26}
\contentsline {section}{\numberline {4.27}Modul pro generov\IeC {\'a}n\IeC {\'\i } VHDL }{30}{section.4.27}
\contentsline {section}{\numberline {4.28}N\IeC {\'a}vrh modulu pro generov\IeC {\'a}n\IeC {\'\i } VHDL}{30}{section.4.28}
\contentsline {chapter}{\numberline {5}Implementace}{31}{chapter.5}
\contentsline {section}{\numberline {5.1}V\IeC {\v s}eobecn\IeC {\'e} informace k implementaci}{31}{section.5.1}
\contentsline {section}{\numberline {5.2}Vstup programu}{31}{section.5.2}
\contentsline {section}{\numberline {5.3}T\IeC {\v r}\IeC {\'\i }da FromFile}{31}{section.5.3}
\contentsline {section}{\numberline {5.4}T\IeC {\v r}\IeC {\'\i }da DoCommand}{31}{section.5.4}
\contentsline {section}{\numberline {5.5}T\IeC {\v r}\IeC {\'\i }da Prikaz}{31}{section.5.5}
\contentsline {section}{\numberline {5.6}STG v programu}{31}{section.5.6}
\contentsline {section}{\numberline {5.7}T\IeC {\v r}\IeC {\'\i }da MakeSG}{34}{section.5.7}
\contentsline {section}{\numberline {5.8}Stuktura stavov\IeC {\'e}ho grafu}{35}{section.5.8}
\contentsline {section}{\numberline {5.9}T\IeC {\v r}\IeC {\'\i }da Region}{37}{section.5.9}
\contentsline {section}{\numberline {5.10}T\IeC {\v r}\IeC {\'\i }da KMap}{37}{section.5.10}
\contentsline {section}{\numberline {5.11}T\IeC {\v r}\IeC {\'\i }da MakeCorLog}{37}{section.5.11}
\contentsline {chapter}{\numberline {6}Testov\IeC {\'a}n\IeC {\'\i }}{39}{chapter.6}
\contentsline {section}{\numberline {6.1}Vstupn\IeC {\'\i } zdroje pro naimplementovan\IeC {\'y} program}{39}{section.6.1}
\contentsline {section}{\numberline {6.2}V\IeC {\'y}stup ATACS}{39}{section.6.2}
\contentsline {section}{\numberline {6.3}Vybran\IeC {\'e} grafy}{39}{section.6.3}
\contentsline {section}{\numberline {6.4}Pr\IeC {\r u}b\IeC {\v e}h synt\IeC {\'e}zy na ATACS}{40}{section.6.4}
\contentsline {section}{\numberline {6.5}V\IeC {\'y}stup z ATACS}{40}{section.6.5}
\contentsline {section}{\numberline {6.6}Pr\IeC {\r u}b\IeC {\v e}h generov\IeC {\'a}n\IeC {\'\i } VHDL k\IeC {\'o}du v naimplementovan\IeC {\'e}m programu}{40}{section.6.6}
\contentsline {section}{\numberline {6.7}V\IeC {\'y}sledn\IeC {\'e} srovn\IeC {\'a}n\IeC {\'\i }}{42}{section.6.7}
\contentsline {section}{\numberline {6.8}\IeC {\v C}asov\IeC {\'a} slo\IeC {\v z}itost }{43}{section.6.8}
\contentsline {section}{\numberline {6.9}Testov\IeC {\'a}n\IeC {\'\i } vstupu }{44}{section.6.9}
\contentsline {section}{\numberline {6.10}Z\IeC {\'a}v\IeC {\v e}r testov\IeC {\'a}n\IeC {\'\i }}{44}{section.6.10}
\contentsline {chapter}{\numberline {7}Simulace}{45}{chapter.7}
\contentsline {section}{\numberline {7.1}Pom\IeC {\r u}cky pro simulaci}{45}{section.7.1}
\contentsline {section}{\numberline {7.2}Postup simulace, vytvo\IeC {\v r}en\IeC {\'\i } simulace}{45}{section.7.2}
\contentsline {section}{\numberline {7.3}Nastaven\IeC {\'\i } Xilinx ISE Simul\IeC {\'a}toru}{45}{section.7.3}
\contentsline {section}{\numberline {7.4}Simulace C-elementu}{47}{section.7.4}
\contentsline {section}{\numberline {7.5}Nastaven\IeC {\'\i } pro C-element}{47}{section.7.5}
\contentsline {section}{\numberline {7.6}V\IeC {\'y}stup simulace pro C-element}{47}{section.7.6}
\contentsline {section}{\numberline {7.7}C-element v FPGA}{49}{section.7.7}
\contentsline {section}{\numberline {7.8}Simulace asynchronn\IeC {\'\i }ho obvodu}{50}{section.7.8}
\contentsline {section}{\numberline {7.9}Z\IeC {\'a}v\IeC {\v e}r simulace}{53}{section.7.9}
\contentsline {chapter}{\numberline {8}Z\IeC {\'a}v\IeC {\v e}r}{55}{chapter.8}
\contentsline {chapter}{\numberline {9}Literatura}{57}{chapter.9}
\contentsline {chapter}{\numberline {A}Seznam pou\IeC {\v z}it\IeC {\'y}ch zkratek}{59}{appendix.A}
\contentsline {chapter}{\numberline {B}U\IeC {\v z}ivatelsk\IeC {\'a} p\IeC {\v r}\IeC {\'\i }ru\IeC {\v c}ka}{61}{appendix.B}
\contentsline {section}{\numberline {B.1}Vstup programu}{61}{section.B.1}
\contentsline {section}{\numberline {B.2}P\IeC {\'\i }\IeC {\v s}eme vstup}{62}{section.B.2}
\contentsline {section}{\numberline {B.3}Spu\IeC {\v s}t\IeC {\v e}n\IeC {\'\i } programu a manipulace}{62}{section.B.3}
\contentsline {chapter}{\numberline {C}Obsah p\IeC {\v r}ilo\IeC {\v z}en\IeC {\'e}ho CD}{63}{appendix.C}
