 
   July 1, 1994                                                        SIS(1)
 
   short_tests [-fFhirtV] [-v verbosity_level] file
 
     Perform test generation for sequential circuits with the goal of produc-
     ing small test sets. Random test generation is not used unless its use
     is specified by the user. Deterministic test generation is accomplished
     by one of two methods. The first method is a three-step test generation
     algorithm consisting of combinational test generation (assuming that
     latch outputs are controllable, and that latch inputs are observable),
     followed by state justification and propagation, when necessary. The
     combinational test generation is accomplished using Boolean satisfiabil-
     ity.  Justification and propagation are performed using implicit state
     transition graph traversal techniques. If the three-step method does not
     generate a test for a fault, then the product of the good and faulty
     circuit is built and traversed, as in sequential circuit verification.
     If this traversal proves the circuits equivalent, then the fault is
     redundant; otherwise any differentiating sequence is a test for the
     fault. Fault simulation is performed after each deterministic test gen-
     eration.
 
     Fault collapsing is performed before test generation, across only simple
     gates. Both fault equivalence and fault dominance are used to reduce the
     fault list.
 
     Deterministically-generated tests may start from the circuit reset state
     or a state reached by the application of another test. In the latter
     case, the new test is appended onto the end of the old test.
 
     Reverse fault simulation is performed as a post-processing step to
     reduce test set size.
 
     The -f option causes the test generator not to perform fault simulation
     of deterministically-generated tests on untested faults.
 
     The -F option causes the test generator not to use reverse fault simula-
     tion.
 
     The -h option restricts the boolean satisfiability algorithm to not use
     non-local implications. Four greedy ordering heuristics are tried in
     this case instead of the default of eight. Hard-to-test faults that can
     only be tested with non-local implication information are aborted by
     this option.
 
     The -i option causes the test generator not to append new tests onto the
     end of old tests.
 
     The -r option causes the test generator to perform random test pattern
     generation and random propagation.
 
     The -t option first converts the network to arbitrary fanin AND and OR
     gates. The decomposed network is returned.
 
     The -v allows the specification of the verbosity level of the output.
 
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   SIS(1)                                                        July 1, 1994
 
     The -V causes the test generator to not use the three-step algorithm to
     generate tests. Instead, only good/faulty product machine verification
     is used to generate tests, thus guaranteeing that each individual test
     generated is the shortest possible.
 
     If file is specified, test patterns are written out to the given file.
 
     Note: in order to use this command with sequential circuits, the circuit
     reset state must be specified in the circuit input file.
 
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