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atpg [-fFhrRpt] [-d RTG_depth] [-n n_fault_sim] [-v verbosity_level] 
     [-y random_prop_depth] file
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Perform test generation for both combinational and sequential circuits using 
random test generation, deterministic test generation, and fault simulation. Deterministic test generation is accomplished by one of two methods. The 
first method is a three-step test generation algorithm consisting of 
combinational test generation (assuming that latch outputs are controllable, 
and that latch inputs are observable), followed by state justification and propagation, when necessary. The combinational test generation is 
accomplished using Boolean satisfiability. Justification and propagation are 
performed using implicit state transition graph traversal techniques. If the 
three-step method does not generate a test for a fault, then the product of 
the good and faulty circuit is built and traversed, as in sequential circuit 
verification. If this traversal proves the circuits equivalent, then the 
fault is redundant; otherwise any differentiating sequence is a test for the 
fault.
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Fault collapsing is performed before test generation, across only simple 
gates. Both fault equivalence and fault dominance are used to reduce the 
fault list.
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For combinational circuits, external don't cares are automatically taken 
into account when the don't care network is attached to the care network. The PI's and PO's of the external don't care network (when it is not NIL) must match exactly with the care network. That is, the don't care network cannot specify only a subset of the PI's or PO's of the care network. If this condition is not met,
then the atpg package automatically adds dummy primary inputs and outputs to the
external don't care network.
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Reverse fault simulation is performed as a post-processing step to reduce
test set size.
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The \fB-f\fP option causes the atpg not to perform fault simulation of 
deterministically-generated tests on untested faults. 
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The \fB-F\fP option causes the atpg not to use reverse fault simulation. 
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The \fB-h\fP option restricts the boolean satisfiability algorithm to not use 
non-local implications. Four greedy ordering heuristics are tried in this case 
instead of the default of eight. Hard-to-test faults that can only be tested 
with non-local implication information are aborted by this option.
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The \fB-r\fP option causes the atpg not to perform random test pattern
generation.
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The \fB-R\fP option causes the atpg not to perform random propagation. 
(Deterministic propagation is still attempted).  
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The \fB-p\fP option causes the atpg not to build any product machines. Thus, 
neither deterministic propagation nor good/faulty product machine traversal
will be performed. 
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The \fB-t\fP option first converts the network to arbitrary fanin AND and
OR gates. The decomposed network is returned.
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The \fB-d\fP option allows the specification of the length of the random
sequences applied during random test generation. The default length is
the depth of the circuit's state transition graph. 
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The \fB-n\fP option allows the specification of the number of sequences
to fault simulate at one time during fault simulation. The default is the
system word length.  
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The \fB-v\fP allows the specification of the verbosity level of the output.
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The \fB-y\fP option allows the specification of the length of the random
sequences applied during random propagation. The default length is 20. 
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If \fBfile\fP is specified, test patterns are written out to the given file.
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Note: in order to use this command with sequential circuits, the circuit
reset state must be specified in the circuit input file.
