.\" /*
.\"  * Revision Control Information
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.\"  * $Source: /vol/opua/opua2/sis/sis-1.1/common/src/sis/sis_lib/help/RCS/xilinx.1,v $
.\"  * $Author: sis $
.\"  * $Revision: 1.2 $
.\"  * $Date: 1992/05/06 19:04:01 $
.\"  *
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.XX
XILINX
.br
Description
.br
.PP
This is a package to optimize the Boolean network and map it onto
the Xilinx Programmable Gate Array architecture
(reference: Xilinx, the Programmable Gate Array Data Book,
Xilinx Corporation).
All the routines except \fBxl_merge\fR can be used to map the design
onto an architecture with a CLB (Configurable Logic Block) realizing an
arbitrary function of up to n inputs,  where n >= 2.
The package contains the following commands available to the user 
for experimentation.
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.PP
Suggested script
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.PP
time
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.PP
sweep
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.PP
simplify
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.PP
sweep
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.PP
simplify
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.PP
xl_split -n  5
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.PP
sweep
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.PP
simplify
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.PP
xl_split -n 5
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.PP
sweep
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.PP
xl_partition -n 5
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.PP
sweep
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.PP
simplify
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.PP
xl_partition -n 5
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.PP
sweep
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.PP
xl_k_decomp -n 5
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.PP
sweep
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.PP
xl_cover -n 5 -h 3
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.PP
xl_merge
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.PP
time
