Major Publications
2005
- Bartosinski R. - Danek M. - Honzik P. - Matousek R.: Dynamic reconfiguration in FPGA-based SoC designs. In Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems. Hungary, Sopron 2005, pp. 129-136.
- Daněk M. - Honzík P. - Kadlec J. - Matoušek R. - Pohl Z.: Reconfigurable system on programmable chip platform. ATMEL Applications Journal, No. 4, (Spring 2005), pp. 9-12
- Fišer, P. - Kubátová, H.: Output Grouping-Based Decomposition of Logic Functions, Proc. 8th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2005 (DDECS'05), Sopron, HU, 13.-16.4.2005, pp. 137-144 pdf
- Fišer, P. - Kubátová, H.: Pseudorandom Testability - Study of the Effect of the Generator Type, Acta Polytechnica, Vol. 2, August 2005, CVUT, ISSN 1210-2709, pp. 47-54 pdf
- Fišer, P. - Kubátová, H.: Improvement of the Fault Coverage of the Pseudo-Random Phase in Column Matching BIST, Proc. 31th Euromicro Symposium on Digital Systems Design (DSD'05), Porto, (Portugal), 30.8. - 3.9.05, pp. 56-63 pdf, slides
- Kafka L. - Kubalík P. - Kubátová H. - Novák O.: Fault Classification for Self-checking Circuits Implemented in FPGA, Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron, 2005, pp. 228-231
- Novotný M. - Schmidt J.: General Digit-Serial Normal Basis Multiplier, In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, s. 99-104. ISBN 963 9364 48 7
2004
- Daněk, M. - Kolář, J.: Timing-Driven Physical Design for FPGAs, Doktorská práce (Ph.D.), Prague: CTU, Faculty of Electrical Engineering, 2004. 176 p.
- Daněk, M. - Kolář, J.: FPGA Modelling for High-Performance Algorithms, In ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays. New York: ACM Press, 2004, pp. 251
- Daněk M. - Honzík P. - Kadlec J. - Matoušek R. - Pohl Z.: Reconfigurable System-on-a-Programmeable-Chip Platform, In Proceedings of IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop. Stará Lesná, SK, 2004, pp. 21-28
- Dobiáš, R. - Grillinger, P. - Racek, S.: Using Markov Models for Evaluation of Single Event Upset in TTP/C Systems, Proc. IFAC Workshop on Programmable Devices and Systems, Gliwice (PL), pp. 100-104
- Dobiáš, R. - Kubátová, H.: FPGA Based Design of Raiway's Interlocking Equipment, Proc. 30th Euromicro Symposium on Digital Systems Design (DSD'04), Rennes (FR), 31.8. - 3.9.04, pp. 467-473
- Fišer, P. - Kubátová, H.: Boolean Minimizer FC-Min: Coverage Finding Process, Proc. 30th Euromicro Symposium on Digital Systems Design (DSD'04), Rennes (FR), 31.8. - 3.9.04, pp. 152-159
- Fišer, P. - Kubátová, H.: An Efficient Mixed-Mode BIST Technique, Proc. 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2004 (DDECS'04), Tatranská Lomnica, SK, 18.-21.4.2004, pp. 227-230
- Fišer, P. - Kubátová, H.: Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST, Proc. 9th Biennial Baltic Electronics Conference (BEC'04), Tallinn (Estonia), 3.-6.10.2004, pp. 201-204 pdf
- Schmidt J. - Novotný M.: Scalable Shifter Synthesis for a Finite Field Arithmetic Unit, In DDECS - Proceedings of 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Stará Lesná: Institute of Informatics, Slovak Akademy of Sciences, Bratislava, 2004, s. 195-198. ISBN 80-969117-9-1
2003
- Fišer, P. - Hlavička, J.: BOOM - A Heuristic Boolean Minimizer, Computers and Informatics, Vol. 22, 2003, No. 1, pp. 19-51 pdf
- Fišer, P. - Hlavička, J. - Kubátová, H.: FC-Min: A Fast Multi-Output Boolean Minimizer, Proc. 29th Euromicro Symposium on Digital Systems Design (DSD'03), Antalya (TR), 1.-6.9.2003, pp. 451-454
- Fišer, P. - Hlavička, J. - Kubátová, H.: Coverage-Directed Assignment Approach to BIST, Proc. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'03), Poznan (Poland), 14.-16.4.2003, pp. 87-92 pdf
- Kubalík P. - Kubátová H.: Design of Self Checking Circuits Based on FPGA, Proceedings of the 15th International Conference on Microelectronics, Cairo, 2003, pp. 378-381
- Schmidt J. - Novotný M.: Scalable Multiplication and Inversion Unit for ECDSA, In Programmable Devices and Systems 2003. Oxford: Elsevier Science, 2003, vol. 1, s. 226-231. ISBN 0-08-044130-0
- Schmidt J. - Novotný M.: Normal Basis Multiplication and Inversion Unit for Elliptic Curve Cryptographhy, In Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems. Piscataway: IEEE, 2003, s. 82-85. ISBN 0-7803-8163-7
2002
- Daněk, M. - Muzikář, Z.: Integrated Iterative Approach to FPGA Placement, In Field-Programmable Logic and Applications (FPL 2002), pp. 253-262
- Daněk, M. - Muzikář, Z.: Integrated Timing-Driven Approach to the FPGA Layout , In The 9th IEEE International Conference on Electronics, Circuits and Systems, 2002, pp. 693-696
- Daněk, M. - Smith, R.E.: XCS Applied to Mapping FPGA Architectures, In GECCO 2002. San Francisco, 2002, pp. 212-219
- Fišer, P.: Minimization of Boolean Functions, MSc. Thesis, Prague, CTU, May 2002, 70 pp. pdf
- Kadlec J. - Matousek R. - Hermanek A. - Licko M. - Tichy M.: Lattice for FPGAs using logarithmic arithmetic. Electronic Engineering Design, 74 (2002), 906, pp. 53-56
- Matousek R. - Tichy M. - Pohl Z. - Kadlec J. - Softley C.: Logarithmic number system and floating-point arithmetics on FPGA. In Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. ( Lecture Notes in Computer Science. 2438). Springer, Berlin 2002, pp. 627-636
- Schmidt J. - Novotný M. - Jäger M. - Bečvář M. - Jáchim M.: Comparison of the Polynomial and Optimal Normal Basis ECDSA for GF(2^162), In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002. Brno: University of Technology, 2002, s. 150-157. ISBN 80-214-2094-4
- Schmidt J. - Novotný M. - Jäger M. - Bečvář M. - Jáchim M.: Exploration of Design Space in ECDSA, In Field-Programmable Logic and Applications - FPL2002
2001
- Bečvář M. - Schmidt J.: Reconfigurable Acceleration of Intel PC: A Quantitative Analysis, In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Gyor: Széchenyi István University of Applied Sciences, 2001, s. 93-96. ISBN 963-7175-16-4
- Fišer, P. - Hlavička, J.: On the Use of Mutations in Boolean Minimization. Proc. Euromicro Symposium on Digital Systems Design, Warsaw (Poland) 4.-6.9.2001, pp. 300-305
- Fišer, P. - Hlavička, J.: Implicant Expansion Method used in the BOOM Minimizer. Proc. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'01), Gyor (Hungary), 18.-20.4.2001, pp. 291-298 pdf
- Hlavička, J. - Fišer, P.: BOOM - a Heuristic Boolean Minimizer. Proc. International Conference on Computer-Aided Design ICCAD 2001, San Jose, California (USA), 4.-8.11.2001, pp. 439-442
1999
- Daněk, M. - Muzikář, Z.: Global Routing Models, In Field-Programmable Logic and Applications, 1999, pp. 391-395