Projects
BOOM-II - A Boolean Minimizer
A heuristic two-level minimizer for Boolean functions with many inputs and outputs
Contact person:
Petr Fišer
BOOM Benchmarks
Set of artificial standard benchmarks
Two-level logic circuits - PLAs
Contact person:
Petr Fišer
PLA Generator
Parametrized generator of random Boolean functions, in the PLA format
Contact person:
Petr Fišer
ColMatch - A BIST design tool
Test-per-clock mixed-mode BIST
Contact person:
Petr Fišer
DZU benchmark database
Database of standard logis synthesis benchmarks
Contact person:
Hana Kubátová
ADAPTMAP - an adaptive mapper for LUT-based FPGAs
General-purpose mapping algorithm that will be able to adapt its behaviour according to user-supplied properties of a target FPGA device
Contact person:
Martin Daněk
Timing-driven physical design algorithms
Implementing and testing a placement / global routing algorithm based on an integrated approach
Contact person:
Martin Daněk
Dynamically reconfigurable FPGAs
FPGA design methodology
Fault tolerant, fail safe and space effective design
Practical implementation in ATMEL products
Contact person:
Martin Daněk
Petri nets
Direct implementation of PN in FPGA
Practical models in Design/CPN and other professional Petri Nets design tools
Contact person:
Hana Kubátová
Optimal FSM implementation in FPGAs
Searching for the properties, parameters and way of finite state machine (FSM) description
Coding and decomposition of FSMs
Optimal implementation of combinational circuits
Contact person:
Hana Kubátová
Arithmetic Hardware for
GF
(2
m
)
Development of arithmetic units that can be scaled according to the given purpose and environment
Interaction between algorithms and FPGA architecture
Application fields – embedded cryptographic systems
Contact person:
Jan Schmidt
Processor architectures
Processor for educational purposes – DOP
Hardware support for garbage collection
Reconfigurable microprogrammed controllers
Contact person:
Miloš Bečvář
Complex EDA system for educational purposes
Experimental Electronic Design Automation software
For testing new algorithms
For simple use
Contact person:
Petr Fišer
,
Jan Schmidt
Atalanta-M
Modified ATALANTA z VirginiaTech
ATPG and fault simulator joined into one tool
Extended interface
Contact person:
Petr Fišer
Past Major Projects
Formal Procedures in Diagnostics of Digital Circuits - Verification of Testable Design
(GA 102/01/1531, 2001-2003)
Built-in Self-test Equipment Optimisation Methods in Integrated Circuits
(GA 102/01/0566, 2001-2003)
Fault Injection for TTA
(OKIX IST-1999-10748, 2000-2002)
Research into Methods for Speeding up Computations Using Reconfigurable Hardware
(GA 102/99/1017, 1999-2001)
Methods and Tools for Testability Analysis of Digital Circuits
(GA 102/98/1463, 1998-2000)
Research and Application of at Built-In Self-Test for IC
(GA 102/98/1003, 1998-2000)
COPRODES - A CAD System for Automatic Design of FPGA-Based Communication Processors
(
EU Copernicus
, 1995-1998)