@CodeTemplate
-- Basic Code Template
-- entity $cntr$
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

-- dollar marks
entity $cntr$ is
port (
    $cntr$_out : out std_logic_vector(3 to 0);
    $cntr$_en : in std_logic;
    $cntr$_count : in std_logic_vector(7 downto 0)
);
end entity;

architecture $cntr$_BODY of cntr is

type T1 is ($state1, state2, state3$);
type NUMERO is ('X', 'Z', '0');
type $state$_T is (WAIT_B0, WAIT_B1, POCITEJ);
signal $state$_act, $state$_next : $state$_T;
constant $cntr$_NEW : stav_T := WAIT_B0;

begin
    -- whole CASE generated by specific SIGNAL type
    DALSI_STAV : process (B0, B1, READY, STAV)
    begin
        #case=state_act{first line
                        second line
                        third line}#	
    end process;

    -- CASE_BODY generated by specific TYPE
    DALSI_STAV : process (B0, B1, READY, STAV)
    begin
	case $state$_next is
                #case_body=$state$_T{
                          first line
                          cntr: $cntr$
                          third line}#
	end case;	
    end process;

end architecture;