@TestbenchTemplate
-- $tbName$ testbench
-- testbench for $entityName$ entity
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

-- name of the testbench
entity $tbName$ is
end entity;

architecture TESTBENCH of $tbName$ is

    -- whole component
    $component$

    -- signals
    $signals$
	
begin

    -- whole instance
    $instance$

    -- name of tested entity
    mojePortMap1 : $entityName$ PORT MAP(
        -- mapping ports to signals
        -- $generic_map$ also could be used
        $port_map$
    );
	
    mojePortMap2 : $entityName$ PORT MAP(
        -- mappings ports to signals "inline"
        -- $generic_map_inline$ also could be used
	$port_map_inline$
    );

    clk_sig : process
    begin 
	CLK<= '1';
	wait for 50 ns;
	CLK <= '0';
	wait for 50 ns;
    end process;

end architecture;