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publication:public_list [2017/03/06 12:01]
xkubalik [2014]
publication:public_list [2017/10/10 12:14] (current)
xkubalik [2003]
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 ====== All publications ====== ====== All publications ======
 +
 +==== 2017 ====
 +
 +  * **Design of a Residue Number System Based Linear System Solver in Hardware**, Buček, J.; Kubalík, P.; Lórencz, R.; Zahradnický,​ T., Journal of Signal Processing Systems. 2016, 1-14. ISSN 1939-8018.
 +
  
 ==== 2016 ==== ==== 2016 ====
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-  * **Design of a Residue Number System Based Linear System Solver in Hardware**, Buček, J.; Kubalík, P.; Lórencz, R.; Zahradnický,​ T., Journal of Signal Processing Systems. 2016, 1-14. ISSN 1939-8018. 
   * **A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time**, Bartík, M.; Ubik, S.; Kubalík, P., In: ReConFig’16. Piscataway: IEEE, 2016, ISBN 978-1-5090-3706-3.   * **A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time**, Bartík, M.; Ubik, S.; Kubalík, P., In: ReConFig’16. Piscataway: IEEE, 2016, ISBN 978-1-5090-3706-3.
   * **Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase**, Bartík, M.; Ubik, S.; Kubalík, P., In: Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016, pp. 89-92. ISBN 978-80-214-5376-0.   * **Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase**, Bartík, M.; Ubik, S.; Kubalík, P., In: Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016, pp. 89-92. ISBN 978-80-214-5376-0.
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    * **Design of Self Checking Circuits Based on FPGA** (Paper in Conference Proceedings) 2003, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 15th International Conference on Microelectronics. Cairo: Cairo University, 2003, p. 378-381. ISBN 977-05-2010-1. {{:​publication:​icm2003.pdf|pdf}}    * **Design of Self Checking Circuits Based on FPGA** (Paper in Conference Proceedings) 2003, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 15th International Conference on Microelectronics. Cairo: Cairo University, 2003, p. 378-381. ISBN 977-05-2010-1. {{:​publication:​icm2003.pdf|pdf}}
      ​* ​ //​__Citation__:​ **"​Design Space Exploration for the Design of Reliable SRAM-Based FPGA Systems"​**,​ Cristiana Bolchini and Antonio Miele, In Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT '08). IEEE Computer Society, Washington, DC, USA, 332-340. 2008.//      ​* ​ //​__Citation__:​ **"​Design Space Exploration for the Design of Reliable SRAM-Based FPGA Systems"​**,​ Cristiana Bolchini and Antonio Miele, In Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT '08). IEEE Computer Society, Washington, DC, USA, 332-340. 2008.//
 +     ​* ​ //​__Citation__:​ **"​Applying partial fault tolerance with explicit area constraints"​**,​ David L. Foster; Darrin M. Hanna, International Journal of Embedded Systems (IJES), Vol. 5, No. 1/2, 2013//
 ===== Main page ===== ===== Main page =====
  
   * [[:​start|Pavel Kubalík'​s Home Page]]   * [[:​start|Pavel Kubalík'​s Home Page]]
publication/public_list.1488798098.txt.gz · Last modified: 2017/03/06 12:01 (external edit)