publication:public_list
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
publication:public_list [2017/01/20 13:50] xkubalik [2009] |
publication:public_list [2017/10/10 12:14] (current) xkubalik [2003] |
||
|---|---|---|---|
| Line 1: | Line 1: | ||
| ====== All publications ====== | ====== All publications ====== | ||
| + | |||
| + | ==== 2017 ==== | ||
| + | |||
| + | * **Design of a Residue Number System Based Linear System Solver in Hardware**, Buček, J.; Kubalík, P.; Lórencz, R.; Zahradnický, T., Journal of Signal Processing Systems. 2016, 1-14. ISSN 1939-8018. | ||
| + | |||
| ==== 2016 ==== | ==== 2016 ==== | ||
| Line 5: | Line 10: | ||
| - | * **Design of a Residue Number System Based Linear System Solver in Hardware**, Buček, J.; Kubalík, P.; Lórencz, R.; Zahradnický, T., Journal of Signal Processing Systems. 2016, 1-14. ISSN 1939-8018. | ||
| * **A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time**, Bartík, M.; Ubik, S.; Kubalík, P., In: ReConFig’16. Piscataway: IEEE, 2016, ISBN 978-1-5090-3706-3. | * **A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time**, Bartík, M.; Ubik, S.; Kubalík, P., In: ReConFig’16. Piscataway: IEEE, 2016, ISBN 978-1-5090-3706-3. | ||
| * **Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase**, Bartík, M.; Ubik, S.; Kubalík, P., In: Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016, pp. 89-92. ISBN 978-80-214-5376-0. | * **Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase**, Bartík, M.; Ubik, S.; Kubalík, P., In: Počítačové Architektury & Diagnostika PAD 2016 - Sborník příspěvků. Brno: Vysoké učení technické v Brně, 2016, pp. 89-92. ISBN 978-80-214-5376-0. | ||
| Line 17: | Line 21: | ||
| ==== 2014 ==== | ==== 2014 ==== | ||
| - | * **System Design of an FPGA Linear Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design, DSD2014, Verona, 2014-08-27/2014-08-29. Linz: Johannes Kepler University, 2014, ISBN 978-3-902457-40-0. | + | * **System Design of an FPGA Linear Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design, DSD2014, Verona, 2014-08-27/2014-08-29. Linz: Johannes Kepler University, 2014, ISBN 978-3-902457-40-0. {{ :publication:dsd14_wip.pdf |pdf}} |
| - | * **System on Chip Design of a Linear System Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R.,. In: 2014 International Symposium on System-on-Chip Proceedings, SoC 2014, Tampere, 2014-10-28/2014-10-29. Piscataway: IEEE, 2014, ISBN 9781479968909. | + | * **System on Chip Design of a Linear System Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R.,. In: 2014 International Symposium on System-on-Chip Proceedings, SoC 2014, Tampere, 2014-10-28/2014-10-29. Piscataway: IEEE, 2014, ISBN 9781479968909. {{ :publication:soc14.pdf |pdf}} |
| - | * **An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R., Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems, ICECS 2014, Marseille, 2014-12-07/2014-12-10. Monterey: IEEE Circuits and Systems Society, 2014, pp. 706-709. ISBN 978-1-4799-4242-8. | + | * **An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R., Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems, ICECS 2014, Marseille, 2014-12-07/2014-12-10. Monterey: IEEE Circuits and Systems Society, 2014, pp. 706-709. ISBN 978-1-4799-4242-8. {{ :publication:icecs14.pdf |pdf}} |
| ==== 2013 ==== | ==== 2013 ==== | ||
| Line 123: | Line 127: | ||
| * **Design of Self Checking Circuits Based on FPGA** (Paper in Conference Proceedings) 2003, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 15th International Conference on Microelectronics. Cairo: Cairo University, 2003, p. 378-381. ISBN 977-05-2010-1. {{:publication:icm2003.pdf|pdf}} | * **Design of Self Checking Circuits Based on FPGA** (Paper in Conference Proceedings) 2003, KUBALÍK P., KUBÁTOVÁ H. In Proceedings of the 15th International Conference on Microelectronics. Cairo: Cairo University, 2003, p. 378-381. ISBN 977-05-2010-1. {{:publication:icm2003.pdf|pdf}} | ||
| * //__Citation__: **"Design Space Exploration for the Design of Reliable SRAM-Based FPGA Systems"**, Cristiana Bolchini and Antonio Miele, In Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT '08). IEEE Computer Society, Washington, DC, USA, 332-340. 2008.// | * //__Citation__: **"Design Space Exploration for the Design of Reliable SRAM-Based FPGA Systems"**, Cristiana Bolchini and Antonio Miele, In Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT '08). IEEE Computer Society, Washington, DC, USA, 332-340. 2008.// | ||
| + | * //__Citation__: **"Applying partial fault tolerance with explicit area constraints"**, David L. Foster; Darrin M. Hanna, International Journal of Embedded Systems (IJES), Vol. 5, No. 1/2, 2013// | ||
| ===== Main page ===== | ===== Main page ===== | ||
| * [[:start|Pavel Kubalík's Home Page]] | * [[:start|Pavel Kubalík's Home Page]] | ||
publication/public_list.1484916634.txt.gz · Last modified: 2017/01/20 13:50 by xkubalik
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 4.0 International
