publication:public_list
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publication:public_list [2017/01/20 13:11] xkubalik [2011] |
publication:public_list [2017/03/06 12:01] xkubalik [2014] |
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| ==== 2014 ==== | ==== 2014 ==== | ||
| - | * **System Design of an FPGA Linear Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design, DSD2014, Verona, 2014-08-27/2014-08-29. Linz: Johannes Kepler University, 2014, ISBN 978-3-902457-40-0. | + | * **System Design of an FPGA Linear Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design, DSD2014, Verona, 2014-08-27/2014-08-29. Linz: Johannes Kepler University, 2014, ISBN 978-3-902457-40-0. {{ :publication:dsd14_wip.pdf |pdf}} |
| - | * **System on Chip Design of a Linear System Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R.,. In: 2014 International Symposium on System-on-Chip Proceedings, SoC 2014, Tampere, 2014-10-28/2014-10-29. Piscataway: IEEE, 2014, ISBN 9781479968909. | + | * **System on Chip Design of a Linear System Solver**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R.,. In: 2014 International Symposium on System-on-Chip Proceedings, SoC 2014, Tampere, 2014-10-28/2014-10-29. Piscataway: IEEE, 2014, ISBN 9781479968909. {{ :publication:soc14.pdf |pdf}} |
| - | * **An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R., Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems, ICECS 2014, Marseille, 2014-12-07/2014-12-10. Monterey: IEEE Circuits and Systems Society, 2014, pp. 706-709. ISBN 978-1-4799-4242-8. | + | * **An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries**, Buček, J., Kubalík, P., Zahradnický, T., Lorencz, R., Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems, ICECS 2014, Marseille, 2014-12-07/2014-12-10. Monterey: IEEE Circuits and Systems Society, 2014, pp. 706-709. ISBN 978-1-4799-4242-8. {{ :publication:icecs14.pdf |pdf}} |
| ==== 2013 ==== | ==== 2013 ==== | ||
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| * //__Citation__: **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// | * //__Citation__: **"GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs"**, Cinzia Bernardeschi, Luca Cassano, Mario G.C.A. Cimino, Andrea Domenici, Journal of Systems Architecture, Volume 59, Issue 10, Part D, November 2013, Pages 1243-1254, ISSN 1383-7621// | ||
| * //__Citation__: **"Safety Automata Network for Interlocking System"**, Trifonov, V.,: Mechanics Transport Communications, Academic journal, 2011.// | * //__Citation__: **"Safety Automata Network for Interlocking System"**, Trifonov, V.,: Mechanics Transport Communications, Academic journal, 2011.// | ||
| - | + | * //__Citation__: **"Modern methods in railway interlocking algorithms design"**, Piotr Kawaleca, Marcin Rżysko, Microprocessors and Microsystems, 2015. ISSN 0141-9331.// | |
| + | * //__Citation__: **"Algorithms and hardware description languages in railway interlocking logic design"**, Piotr Kawalec, Marcin Rżysko, 13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems — PDES 2015, vol. 48, no. 4, pp. 498 - 503, 2015.// | ||
| ==== 2008 ==== | ==== 2008 ==== | ||
publication/public_list.txt · Last modified: 2017/10/10 12:14 by xkubalik
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