@MANUAL{iso690,
	organization = "\'U\v rad pro technickou normalizaci, metrologii a st\'atn\'\i{} zku\v sebnictv\'\i{}",
	title = "\v CSN ISO 690 Informace a dokumentace -- Pravidla pro bibliografick\'e odkazy a citace informa\v cn\'\i{}ch zdroj{\r u}",
	year = "2011"
}

@ARTICLE{refactor,
    author  = "{S. Chatterjee, A. Mishchenko, and R. Brayton}",
    title   = "{Factor cuts}",
    year    = "{2009}",
    month   = "{Nov.}",
    journal = "{Proc. ICCAD}",
    url     = "{http://www.eecs.berkeley.edu/~alanmi/publications/2006/iccad06_cut.pdf}"
}

@ARTICLE{NPH1,
    author  = "{G. Ausiello et al.}",
    title   = "{Complexity and Approximation}",
    year    = "{1999}",
    month   = "{Nov.}",
    journal = "{Springer}"
}

@ARTICLE{NPH2,
    author  = "{A. Mishchenko, S. Chatterjee, and R. Brayton}",
    title   = "{Computers and Intractability, A Guide to the Theory of NP-Completeness}",
    year    = "1990",
    journal = "{W. H. Freeman \& Co. New York}"
}

@ARTICLE{Balance,
    author  = "{A. Mishchenko, S. Chatterjee, and R. Brayton}",
    title   = "Delay optimization using SOP balancing",
    year    = "2011",
    journal = "International Workshop on Logic and Synthesis",
    url		= "http://www.eecs.berkeley.edu/~alanmi/publications/2011/iccad11_sop.pdf"
}

@ARTICLE{Rewriting,
    author  = "{A. Mishchenko, R. Brayton, S. Jang, and V. Kravets}",
    title   = "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis",
    journal = "International Conference on Computer-Aided Design",
    year    = "2006",
    url		= "http://www.eecs.berkeley.edu/~alanmi/publications/2006/dac06_rwr.pdf"
}

@mastersthesis{ClaudeShannon,
    author    = "Shannon, C. E",
    title     = "A Symbolic Analysis of Relay and Switching Circuits",
    school    = "Massachusetts Institute of Technology",
    year      = "1940"
}

@ARTICLE{McCluskey,
    author  = "{McCluskey, E.J., Jr.}",
    journal = "Bell System Technical Journal",
    title   = "Minimization of Boolean Functions.",
    year    = "1956"
}

@MANUAL{KMAP,
    organization = "{The University of Texas at Dallas}",
    title   = "A Symbolic Analysis of Relay and Switching Circuits",
    year    = "2012",
    url		= "http://www.utdallas.edu/~dodge/EE2310/lec5.pdf"
}

@misc{PLA,
  title={Electrically programmable logic circuits},
  author={D, G.},
  url={http://www.google.com/patents/US3818452},
  year={1974},
  month=jun # "~18",
  publisher={Google Patents},
  note={US Patent 3,818,452}
}

@ARTICLE{NPCoptimization,
    author  = "{Kurt Keutzer}",
    title	= "{Technology Binding and Local Optimization by DAG Matching}",
    url     = "{http://janders.eecg.toronto.edu/1387/readings/dagon.pdf}",
    year    = "{1988}",
    pages	= "{344}",
    journal = "{Design Automation, 1987. 24th Conference on}"
}
@inproceedings{Xinproceedings,
	author		= "Kurt Keutzer",
	title		= "Quality of Tree Matching",
	booktitle	= "{DAGON: Technology Binding and Local Optimization by DAG Matching}",
	year		= "1988"
}

@ARTICLE{Heuristics,
    author  = "{Petr Fi{\v s}er, Jan Schmidt, Ji{\v r}{\' i} Balc{\' a}rek}",
    title   = "Sources of Bias in EDA Tools and Its Influence",
    year    = "1988",
    pages	= "344",
    journal = "{Design and Diagnostics of Electronic Circuits and Systems, 17th International Symposium on}",
    url		= "http://users.fit.cvut.cz/~fiserp/papers/ddecs14.pdf"
}

@MANUAL{ABCTutorial,
    organization = "{Berkeley Logic Synthesis and Verification Group}",
    title   = "Constructing AIGs in ABC",
    year    = "2007",
    url		= "{http://www.eecs.berkeley.edu/~alanmi/abc/aig.pdf}"
}

@MANUAL{ABCprogramming,
    organization = "{Berkeley Logic Synthesis and Verification Group}",
    title   = "Quick Look under the Hood of ABC",
    year    = "2006",
    url		= "{http://www.eecs.berkeley.edu/~alanmi/abc/programming.pdf}"
}

@misc{web:ABCOfficial,
      author = "Berkeley Logic Synthesis and Verification Group",
      title = "ABC: A System for Sequential Synthesis and Verification",
      url = "{http://www.eecs.berkeley.edu/~alanmi/abc/}"
}

@MANUAL{HunNotation,
    organization = "{Microsoft Corporation}",
    title   = "Hungarian Notation",
    year    = "1999",
    url		= "{https://msdn.microsoft.com/en-us/library/aa260976(v=vs.60).aspx}"
}

@misc{web:ABCGit,
      author = "Berkeley Logic Synthesis and Verification Group",
      title = "ABC: System for Sequential Logic Synthesis and Formal Verification",
      url = "{https://bitbucket.org/alanmi/abc}",
      year = "2015",
      month = "April"
}

@MANUAL{qsort,
    organization = "{cplusplus.com}",
    title   = "qsort",
    url		= "{http://www.cplusplus.com/reference/cstdlib/qsort/}"
}

@ARTICLE{BDD,
    author  = "{Randal E. Bryant}",
    title   = "{Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams}",
    year    = "1992",
    pages   = "{2-3}",
    journal = "ACM Computing Surveys, 24, 3, 293- 318"
}

@ARTICLE{BDD1,
    author  = "{S. B. Akers}",
    title   = "{Binary Decision Diagrams}",
    year    = "{1978}",
    pages   = "{509-516}",
    month   = "{June}",
    journal = "{IEEE Transactions on Computers, vol. C-27, No. 6}"
}

@ARTICLE{BDD2,
    author  = "{R. E. Bryant}",
    title   = "{Graph Based Algorithms for Boolean Function Manipulation}",
    year    = "{1986}",
    pages   = "{677-691}",
    month   = "{August}",
    journal = "{ACM Computing Surveys, 24, 3, 293- 318, Vol. 35}"
}

@book{RTL,
    author    = "Frank Vahid",
    title     = "Digital Design with RTL Design, Verilog and VHDL (2nd ed.)",
    publisher = "John Wiley and Sons.",
    year      = "2010"
}

@MANUAL{rndshuffle,
    organization = "{cplusplus.com}",
    title   = "{random\_shuffle}",
    url   = "{http://www.cplusplus.com/reference/algorithm/random_shuffle/}"
}
