Asynch_DIMS
===========
	- Synthesis of asynchronous multilevel circuits, based on DIMS architecture
	- only reports the complexity of the final design
	- for ASYNC'10, DSD'10

Asynch_Multilevel
=================
	- Synthesis of asynchronous multilevel circuits, based on nodes having orthogonal terms
	- only reports the complexity of the final design
	- for DESDes'09
	
BlowupNetwork
=============
	- Artificially enlarges the network, without changing its function
	
BOOM
====
	- Two-level Boolean minimizer
	
GetInfo
=======
	- Displays information on PLA and Blif files
	
GroupOutputs
============
	- Performs FC-Min based (or random) output grouping 
	- Accepts PLA as an input, generates the grouping file
	
MergePLAs
=========
	- Just merges term of two PLAs
	
Negate
======
	- appends inverters to the circuit outputs. PLA->Blif.
	
Ortho
=====
	- Orthogonalization of PLAs (DSOP synthesis)
	
Parity
======
	- Appends a XOR tree to a network in Blif
	
Resynth
=======
	- Resynthesis by parts.
	- Repeatedly extracts parts of the network, minimizes them, and returns back
	- for IWLS'10
	
Resynth_order
=============
	- repeated resynthesis with different orders of nodes, PIs and POs
	
SL_Partition
============
	- Single-level partitioning
	- According the grouping file obtained from GroupOutputs splits a PLA into groups, by outputs
	
Split
=====
	- Splits a PLA obtained by PLA_op::JoinPLAsByInputs, or by Swap project
	
Split_outputs
=============
	- Splits a multi-output PLA into single-input PLAs
	
Strip_udc
=========
	- Removes unreachable don't cares from a PLA and saves them to a separate file
	- for DDECS'09
	
Swap
====
	- Swaps the on- and off-set

Test
====
	- Just for testing purposes
