sis> UC Berkeley, SIS 1.3.6 (compiled 2007-07-18 12:59:37)
sis> <-- START --> 
sis> sis> <-- bbara --> 
sis> sis> sis> fsmenc_output 	pi= 4	po= 2	nodes=  9	latches= 3
lits(sop)=  56	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 322.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbsse --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 19	latches= 4
lits(sop)= 123	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 542.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbtas --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  6	latches= 3
lits(sop)=  32	#states(STG)=   6
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 219.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- beecount --> 
sis> sis> sis> fsmenc_output 	pi= 3	po= 4	nodes=  8	latches= 2
lits(sop)=  31	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 180.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- cse --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 27	latches= 4
lits(sop)= 215	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 767.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk14 --> 
sis> sis> sis> fsmenc_output 	pi= 3	po= 5	nodes= 12	latches= 3
lits(sop)=  81	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 460.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk15 --> 
sis> sis> sis> fsmenc_output 	pi= 3	po= 5	nodes=  9	latches= 2
lits(sop)=  69	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 370.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk16 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 3	nodes= 25	latches= 5
lits(sop)= 291	#states(STG)=  27
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1295.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk17 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 3	nodes=  6	latches= 3
lits(sop)=  59	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 358.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk27 --> 
sis> sis> sis> fsmenc_output 	pi= 1	po= 2	nodes=  5	latches= 3
lits(sop)=  23	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 196.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex1 --> 
sis> sis> sis> fsmenc_output 	pi= 9	po=19	nodes= 39	latches= 5
lits(sop)= 219	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 874.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex3 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  8	latches= 3
lits(sop)=  34	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 219.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex4 --> 
sis> sis> sis> fsmenc_output 	pi= 6	po= 9	nodes= 15	latches= 4
lits(sop)=  78	#states(STG)=  14
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 433.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex5 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  4	latches= 2
lits(sop)=  22	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 155.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex6 --> 
sis> sis> sis> fsmenc_output 	pi= 5	po= 8	nodes= 14	latches= 3
lits(sop)=  97	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 464.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex7 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  4	latches= 2
lits(sop)=  22	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 168.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- keyb --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 2	nodes= 25	latches= 5
lits(sop)= 236	#states(STG)=  19
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 747.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion9 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  16	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 131.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  15	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 120.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mark1 --> 
sis> sis> sis> fsmenc_output 	pi= 5	po=16	nodes= 19	latches= 4
lits(sop)=  78	#states(STG)=  12
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 378.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mc --> 
sis> sis> sis> fsmenc_output 	pi= 3	po= 5	nodes=  6	latches= 2
lits(sop)=  23	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 154.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- opus --> 
sis> sis> sis> fsmenc_output 	pi= 5	po= 6	nodes= 16	latches= 4
lits(sop)=  93	#states(STG)=   9
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 490.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s1 --> 
sis> sis> sis> fsmenc_output 	pi= 8	po= 6	nodes= 30	latches= 5
lits(sop)= 227	#states(STG)=  20
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 991.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s208 --> 
sis> sis> sis> fsmenc_output 	pi=11	po= 2	nodes= 11	latches= 5
lits(sop)=  66	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 355.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s27 --> 
sis> sis> sis> fsmenc_output 	pi= 4	po= 1	nodes=  7	latches= 3
lits(sop)=  30	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 205.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s298 --> 
sis> sis> sis> fsmenc_output 	pi= 3	po= 6	nodes=161	latches= 8
lits(sop)=1986	#states(STG)= 135
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 6375.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s386 --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 18	latches= 4
lits(sop)= 114	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 513.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s420 --> 
sis> sis> sis> fsmenc_output 	pi=19	po= 2	nodes= 11	latches= 5
lits(sop)=  66	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 355.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s510 --> 
sis> sis> sis> fsmenc_output 	pi=19	po= 7	nodes= 25	latches= 6
lits(sop)= 281	#states(STG)=  47
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1241.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s820 --> 
sis> sis> sis> fsmenc_output 	pi=18	po=19	nodes= 52	latches= 5
lits(sop)= 364	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1246.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s832 --> 
sis> sis> sis> fsmenc_output 	pi=18	po=19	nodes= 42	latches= 5
lits(sop)= 340	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1180.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sand --> 
sis> sis> sis> fsmenc_output 	pi=11	po= 9	nodes= 81	latches= 5
lits(sop)= 726	#states(STG)=  32
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 2357.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- shiftreg --> 
sis> sis> sis> fsmenc_output 	pi= 1	po= 1	nodes=  0	latches= 3
lits(sop)=   0	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 90.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sse --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 19	latches= 4
lits(sop)= 123	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 542.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- tav --> 
sis> sis> sis> fsmenc_output 	pi= 4	po= 4	nodes=  8	latches= 2
lits(sop)=  27	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 164.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tbk --> 
sis> sis> sis> fsmenc_output 	pi= 6	po= 3	nodes= 21	latches= 4
lits(sop)= 260	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 883.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train11 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  11	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 108.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train4 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  13	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 104.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
