sis> UC Berkeley, SIS 1.3.6 (compiled 2007-07-18 12:59:37)
sis> <-- START --> 
sis> sis> <-- bbara --> 
sis> sis> sis> jedi_output   	pi= 4	po= 2	nodes= 13	latches= 7
lits(sop)=  63	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 480.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbsse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 27	latches=13
lits(sop)= 127	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 828.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbtas --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  9	latches= 6
lits(sop)=  29	#states(STG)=   6
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 284.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- beecount --> 
sis> sis> sis> jedi_output   	pi= 3	po= 4	nodes=  8	latches= 4
lits(sop)=  30	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 235.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- cse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 48	latches=16
lits(sop)= 221	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1098.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk14 --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes= 28	latches= 7
lits(sop)= 139	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 600.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk15 --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes= 15	latches= 4
lits(sop)=  76	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 426.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk16 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 3	nodes= 70	latches=27
lits(sop)= 279	#states(STG)=  27
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1444.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk17 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 3	nodes= 18	latches= 8
lits(sop)=  82	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 519.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk27 --> 
sis> sis> sis> jedi_output   	pi= 1	po= 2	nodes=  9	latches= 7
lits(sop)=  29	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 320.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex1 --> 
sis> sis> sis> jedi_output   	pi= 9	po=19	nodes= 64	latches=18
lits(sop)= 219	#states(STG)=  18
sis> sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex3 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  7	latches= 5
lits(sop)=  32	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 293.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex4 --> 
sis> sis> sis> jedi_output   	pi= 6	po= 9	nodes= 17	latches=14
lits(sop)=  40	#states(STG)=  14
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 552.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex5 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  5	latches= 4
lits(sop)=  21	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 205.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex6 --> 
sis> sis> sis> jedi_output   	pi= 5	po= 8	nodes= 19	latches= 8
lits(sop)=  98	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 642.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex7 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  4	latches= 3
lits(sop)=  23	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 197.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- keyb --> 
sis> sis> sis> jedi_output   	pi= 7	po= 2	nodes= 50	latches=19
lits(sop)= 254	#states(STG)=  19
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1244.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion9 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  6	latches= 4
lits(sop)=  20	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 203.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  5	latches= 4
lits(sop)=  23	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 216.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mark1 --> 
sis> sis> sis> jedi_output   	pi= 5	po=16	nodes= 28	latches=12
lits(sop)=  80	#states(STG)=  12
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 594.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mc --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes=  9	latches= 4
lits(sop)=  32	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 269.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- opus --> 
sis> sis> sis> jedi_output   	pi= 5	po= 6	nodes= 17	latches= 9
lits(sop)=  75	#states(STG)=   9
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 567.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s1 --> 
sis> sis> sis> jedi_output   	pi= 8	po= 6	nodes= 77	latches=20
lits(sop)= 351	#states(STG)=  20
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1759.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s208 --> 
sis> sis> sis> jedi_output   	pi=11	po= 2	nodes= 25	latches=18
lits(sop)=  81	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 749.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s27 --> 
sis> sis> sis> jedi_output   	pi= 4	po= 1	nodes=  7	latches= 5
lits(sop)=  54	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 343.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s386 --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 31	latches=13
lits(sop)= 126	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 798.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s420 --> 
sis> sis> sis> jedi_output   	pi=19	po= 2	nodes= 25	latches=18
lits(sop)=  81	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 749.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s820 --> 
sis> sis> sis> jedi_output   	pi=18	po=19	nodes= 60	latches=24
lits(sop)= 278	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1476.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s832 --> 
sis> sis> sis> jedi_output   	pi=18	po=19	nodes= 63	latches=24
lits(sop)= 287	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1471.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sand --> 
sis> sis> sis> jedi_output   	pi=11	po= 9	nodes= 99	latches=32
lits(sop)= 477	#states(STG)=  32
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 2760.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- shiftreg --> 
sis> sis> sis> jedi_output   	pi= 1	po= 1	nodes= 15	latches= 8
lits(sop)=  40	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 313.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 27	latches=13
lits(sop)= 127	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 828.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- styr --> 
sis> sis> sis> jedi_output   	pi= 9	po=10	nodes=113	latches=30
lits(sop)= 489	#states(STG)=  30
sis> sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tav --> 
sis> sis> sis> jedi_output   	pi= 4	po= 4	nodes=  5	latches= 4
lits(sop)=  21	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 209.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tbk --> 
sis> sis> sis> jedi_output   	pi= 6	po= 3	nodes= 52	latches=15
lits(sop)= 223	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 985.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train4 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  6	latches= 4
lits(sop)=  19	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 174.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
