sis> UC Berkeley, SIS 1.3.6 (compiled 2007-07-18 12:59:37)
sis> <-- START --> 
sis> sis> <-- bbara --> 
sis> sis> sis> fsmenc_output 	pi= 4	po= 2	nodes=  7	latches= 3
lits(sop)=  48	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 284.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbsse --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 17	latches= 4
lits(sop)= 123	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 511.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbtas --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  7	latches= 3
lits(sop)=  25	#states(STG)=   6
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 187.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- beecount --> 
sis> sis> sis> fsmenc_output 	pi= 3	po= 4	nodes=  7	latches= 2
lits(sop)=  25	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 170.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- cse --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 33	latches= 5
lits(sop)= 214	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 762.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk27 --> 
sis> sis> sis> fsmenc_output 	pi= 1	po= 2	nodes=  6	latches= 4
lits(sop)=  30	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 245.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- lion9 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  13	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 119.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  4	latches= 2
lits(sop)=  15	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 126.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mc --> 
sis> sis> sis> fsmenc_output 	pi= 3	po= 5	nodes=  6	latches= 2
lits(sop)=  25	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 173.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s27 --> 
sis> sis> sis> fsmenc_output 	pi= 4	po= 1	nodes=  6	latches= 3
lits(sop)=  31	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 206.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s386 --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 19	latches= 4
lits(sop)= 128	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 560.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s510 --> 
sis> sis> sis> fsmenc_output 	pi=19	po= 7	nodes= 35	latches= 6
lits(sop)= 302	#states(STG)=  47
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1333.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s820 --> 
sis> sis> sis> fsmenc_output 	pi=18	po=19	nodes= 52	latches= 7
lits(sop)= 343	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1247.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s832 --> 
sis> sis> sis> fsmenc_output 	pi=18	po=19	nodes= 49	latches= 7
lits(sop)= 362	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1240.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- shiftreg --> 
sis> sis> sis> fsmenc_output 	pi= 1	po= 1	nodes=  5	latches= 4
lits(sop)=  37	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 284.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sse --> 
sis> sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 17	latches= 4
lits(sop)= 123	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 511.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- tav --> 
sis> sis> sis> fsmenc_output 	pi= 4	po= 4	nodes=  7	latches= 2
lits(sop)=  24	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 152.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tbk --> 
sis> sis> sis> fsmenc_output 	pi= 6	po= 3	nodes= 51	latches=15
lits(sop)= 224	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 995.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train11 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  12	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 107.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train4 --> 
sis> sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  4	latches= 2
lits(sop)=  14	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 110.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
