sis> UC Berkeley, SIS 1.3.6 (compiled 2007-07-18 12:59:37)
sis> <-- START --> 
sis> sis> <-- bbara --> 
sis> sis> sis> jedi_output   	pi= 4	po= 2	nodes=  7	latches= 3
lits(sop)=  61	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 326.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbsse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 21	latches= 4
lits(sop)= 131	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 592.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbtas --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  7	latches= 3
lits(sop)=  28	#states(STG)=   6
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 201.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- beecount --> 
sis> sis> sis> jedi_output   	pi= 3	po= 4	nodes=  7	latches= 2
lits(sop)=  30	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 177.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- cse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 24	latches= 4
lits(sop)= 245	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 879.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk14 --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes= 12	latches= 3
lits(sop)= 102	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 525.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk15 --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes=  8	latches= 2
lits(sop)=  69	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 352.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk16 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 3	nodes= 31	latches= 5
lits(sop)= 328	#states(STG)=  27
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1396.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk17 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 3	nodes=  8	latches= 3
lits(sop)=  62	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 342.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk27 --> 
sis> sis> sis> jedi_output   	pi= 1	po= 2	nodes=  6	latches= 3
lits(sop)=  26	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 196.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex1 --> 
sis> sis> sis> jedi_output   	pi= 9	po=19	nodes= 44	latches= 5
lits(sop)= 299	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1137.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex3 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  6	latches= 3
lits(sop)=  29	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 218.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex4 --> 
sis> sis> sis> jedi_output   	pi= 6	po= 9	nodes= 14	latches= 4
lits(sop)=  66	#states(STG)=  14
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 407.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex5 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  3	latches= 2
lits(sop)=  22	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 158.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex6 --> 
sis> sis> sis> jedi_output   	pi= 5	po= 8	nodes= 15	latches= 3
lits(sop)= 100	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 478.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex7 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  4	latches= 2
lits(sop)=  26	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 188.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- lion9 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  15	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 131.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  14	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 127.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mark1 --> 
sis> sis> sis> jedi_output   	pi= 5	po=16	nodes= 18	latches= 4
lits(sop)=  95	#states(STG)=  12
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 445.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mc --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes=  7	latches= 2
lits(sop)=  22	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 149.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- opus --> 
sis> sis> sis> jedi_output   	pi= 5	po= 6	nodes= 14	latches= 4
lits(sop)=  81	#states(STG)=   9
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 417.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s208 --> 
sis> sis> sis> jedi_output   	pi=11	po= 2	nodes= 12	latches= 5
lits(sop)= 116	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 570.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s27 --> 
sis> sis> sis> jedi_output   	pi= 4	po= 1	nodes=  7	latches= 3
lits(sop)=  36	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 237.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s386 --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 20	latches= 4
lits(sop)= 138	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 564.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s420 --> 
sis> sis> sis> jedi_output   	pi=19	po= 2	nodes= 12	latches= 5
lits(sop)= 116	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 570.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s510 --> 
sis> sis> sis> jedi_output   	pi=19	po= 7	nodes= 61	latches= 6
lits(sop)= 507	#states(STG)=  47
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1978.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s820 --> 
sis> sis> sis> jedi_output   	pi=18	po=19	nodes= 52	latches= 5
lits(sop)= 402	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1383.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s832 --> 
sis> sis> sis> jedi_output   	pi=18	po=19	nodes= 55	latches= 5
lits(sop)= 438	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1461.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sand --> 
sis> sis> sis> jedi_output   	pi=11	po= 9	nodes=119	latches= 6
lits(sop)= 786	#states(STG)=  32
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 2492.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- shiftreg --> 
sis> sis> sis> jedi_output   	pi= 1	po= 1	nodes=  5	latches= 3
lits(sop)=  36	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 260.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 18	latches= 4
lits(sop)= 135	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 638.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- tav --> 
sis> sis> sis> jedi_output   	pi= 4	po= 4	nodes=  8	latches= 2
lits(sop)=  28	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 164.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tbk --> 
sis> sis> sis> jedi_output   	pi= 6	po= 3	nodes= 23	latches= 4
lits(sop)= 273	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 930.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train11 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  4	latches= 2
lits(sop)=  16	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 126.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train4 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  12	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 110.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
