sis> UC Berkeley, SIS 1.3.6 (compiled 2007-07-18 12:59:37)
sis> <-- START --> 
sis> sis> <-- bbara --> 
sis> sis> fsmenc_output 	pi= 4	po= 2	nodes=  5	latches= 3
lits(sop)=  78	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 395.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbsse --> 
sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 11	latches= 4
lits(sop)= 304	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1040.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbtas --> 
sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  5	latches= 3
lits(sop)=  42	#states(STG)=   6
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 278.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- beecount --> 
sis> sis> fsmenc_output 	pi= 3	po= 4	nodes=  6	latches= 2
lits(sop)=  73	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 348.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- cse --> 
sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 12	latches= 5
lits(sop)= 640	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1873.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk27 --> 
sis> sis> fsmenc_output 	pi= 1	po= 2	nodes=  6	latches= 4
lits(sop)=  45	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 311.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- keyb --> 
sis> sis> fsmenc_output 	pi= 7	po= 2	nodes=  7	latches= 5
lits(sop)=1386	#states(STG)=  19
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 3630.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion9 --> 
sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  18	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 143.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion --> 
sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  24	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 170.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mc --> 
sis> sis> fsmenc_output 	pi= 3	po= 5	nodes=  7	latches= 2
lits(sop)=  71	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 312.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- planet1 --> 
sis> sis> fsmenc_output 	pi= 7	po=19	nodes= 26	latches= 7
lits(sop)=3323	#states(STG)=  48
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 9106.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- planet --> 
sis> sis> fsmenc_output 	pi= 7	po=19	nodes= 26	latches= 7
lits(sop)=3323	#states(STG)=  48
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 9106.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s27 --> 
sis> sis> fsmenc_output 	pi= 4	po= 1	nodes=  4	latches= 3
lits(sop)=  66	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 362.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s298 --> 
sis> sis> fsmenc_output 	pi= 3	po= 6	nodes= 17	latches=11
lits(sop)=9116	#states(STG)= 135
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 25196.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s386 --> 
sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 11	latches= 4
lits(sop)= 326	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1131.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s510 --> 
sis> sis> fsmenc_output 	pi=19	po= 7	nodes= 13	latches= 6
lits(sop)= 793	#states(STG)=  47
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 2860.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s820 --> 
sis> sis> fsmenc_output 	pi=18	po=19	nodes= 26	latches= 7
lits(sop)= 913	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 2943.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s832 --> 
sis> sis> fsmenc_output 	pi=18	po=19	nodes= 26	latches= 7
lits(sop)= 822	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 2631.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- shiftreg --> 
sis> sis> fsmenc_output 	pi= 1	po= 1	nodes=  5	latches= 4
lits(sop)=  49	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 336.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sse --> 
sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 11	latches= 4
lits(sop)= 304	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1040.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- styr --> 
sis> sis> fsmenc_output 	pi= 9	po=10	nodes= 16	latches= 6
lits(sop)=1864	#states(STG)=  30
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 5429.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tav --> 
sis> sis> fsmenc_output 	pi= 4	po= 4	nodes=  6	latches= 2
lits(sop)=  32	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 189.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tbk --> 
sis> sis> fsmenc_output 	pi= 6	po= 3	nodes= 18	latches=15
lits(sop)= 602	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 2635.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train11 --> 
sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  18	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 136.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train4 --> 
sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  29	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 185.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
