sis> UC Berkeley, SIS 1.3.6 (compiled 2007-07-18 12:59:37)
sis> <-- START --> 
sis> sis> <-- bbara --> 
sis> sis> sis> bbara.kiss2.esp	pi= 4	po= 2	nodes=  8	latches= 3
lits(sop)=  49	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: bbara.kiss2.esp, Power = 278.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbsse --> 
sis> sis> sis> bbsse.kiss2.esp	pi= 7	po= 7	nodes= 18	latches= 4
lits(sop)= 109	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: bbsse.kiss2.esp, Power = 505.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbtas --> 
sis> sis> sis> bbtas.kiss2.esp	pi= 2	po= 2	nodes=  6	latches= 3
lits(sop)=  26	#states(STG)=   6
sis> Combinational power estimation, with Zero delay model.
Network: bbtas.kiss2.esp, Power = 197.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- beecount --> 
sis> sis> sis> beecount.kiss2.esp	pi= 3	po= 4	nodes=  6	latches= 2
lits(sop)=  29	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: beecount.kiss2.esp, Power = 185.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- cse --> 
sis> sis> sis> cse.kiss2.esp 	pi= 7	po= 7	nodes= 26	latches= 4
lits(sop)= 189	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: cse.kiss2.esp, Power = 682.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk14 --> 
sis> sis> sis> dk14.kiss2.esp	pi= 3	po= 5	nodes= 11	latches= 3
lits(sop)=  77	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: dk14.kiss2.esp, Power = 422.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk15 --> 
sis> sis> sis> dk15.kiss2.esp	pi= 3	po= 5	nodes=  8	latches= 2
lits(sop)=  68	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: dk15.kiss2.esp, Power = 357.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk16 --> 
sis> sis> sis> dk16.kiss2.esp	pi= 2	po= 3	nodes= 27	latches= 5
lits(sop)= 277	#states(STG)=  27
sis> Combinational power estimation, with Zero delay model.
Network: dk16.kiss2.esp, Power = 1227.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk17 --> 
sis> sis> sis> dk17.kiss2.esp	pi= 2	po= 3	nodes=  8	latches= 3
lits(sop)=  64	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: dk17.kiss2.esp, Power = 359.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk27 --> 
sis> sis> sis> dk27.kiss2.esp	pi= 1	po= 2	nodes=  6	latches= 3
lits(sop)=  26	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: dk27.kiss2.esp, Power = 196.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex1 --> 
sis> sis> sis> ex1.kiss2.esp 	pi= 9	po=19	nodes= 39	latches= 5
lits(sop)= 214	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: ex1.kiss2.esp, Power = 899.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex3 --> 
sis> sis> sis> ex3.kiss2.esp 	pi= 2	po= 2	nodes=  6	latches= 3
lits(sop)=  25	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: ex3.kiss2.esp, Power = 192.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex4 --> 
sis> sis> sis> ex4.kiss2.esp 	pi= 6	po= 9	nodes= 19	latches= 4
lits(sop)=  74	#states(STG)=  14
sis> Combinational power estimation, with Zero delay model.
Network: ex4.kiss2.esp, Power = 404.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex5 --> 
sis> sis> sis> ex5.kiss2.esp 	pi= 2	po= 2	nodes=  4	latches= 2
lits(sop)=  15	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: ex5.kiss2.esp, Power = 125.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex6 --> 
sis> sis> sis> ex6.kiss2.esp 	pi= 5	po= 8	nodes= 16	latches= 3
lits(sop)=  86	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: ex6.kiss2.esp, Power = 442.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex7 --> 
sis> sis> sis> ex7.kiss2.esp 	pi= 2	po= 2	nodes=  4	latches= 2
lits(sop)=  20	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: ex7.kiss2.esp, Power = 157.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- keyb --> 
sis> sis> sis> keyb.kiss2.esp	pi= 7	po= 2	nodes= 27	latches= 5
lits(sop)= 234	#states(STG)=  19
sis> Combinational power estimation, with Zero delay model.
Network: keyb.kiss2.esp, Power = 793.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion9 --> 
sis> sis> sis> lion9.kiss2.esp	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  16	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: lion9.kiss2.esp, Power = 130.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion --> 
sis> sis> sis> lion.kiss2.esp	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  13	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: lion.kiss2.esp, Power = 121.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mark1 --> 
sis> sis> sis> mark1.kiss2.esp	pi= 5	po=16	nodes= 18	latches= 4
lits(sop)=  93	#states(STG)=  12
sis> Combinational power estimation, with Zero delay model.
Network: mark1.kiss2.esp, Power = 405.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mc --> 
sis> sis> sis> mc.kiss2.esp  	pi= 3	po= 5	nodes=  7	latches= 2
lits(sop)=  27	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: mc.kiss2.esp, Power = 167.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- opus --> 
sis> sis> sis> opus.kiss2.esp	pi= 5	po= 6	nodes= 14	latches= 4
lits(sop)=  83	#states(STG)=   9
sis> Combinational power estimation, with Zero delay model.
Network: opus.kiss2.esp, Power = 452.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s1 --> 
sis> sis> sis> s1.kiss2.esp  	pi= 8	po= 6	nodes= 31	latches= 5
lits(sop)= 243	#states(STG)=  20
sis> Combinational power estimation, with Zero delay model.
Network: s1.kiss2.esp, Power = 1089.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s208 --> 
sis> sis> sis> s208.kiss2.esp	pi=11	po= 2	nodes= 12	latches= 5
lits(sop)=  70	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: s208.kiss2.esp, Power = 359.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s27 --> 
sis> sis> sis> s27.kiss2.esp 	pi= 4	po= 1	nodes=  4	latches= 3
lits(sop)=  23	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: s27.kiss2.esp, Power = 164.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s386 --> 
sis> sis> sis> s386.kiss2.esp	pi= 7	po= 7	nodes= 18	latches= 4
lits(sop)= 115	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: s386.kiss2.esp, Power = 511.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s420 --> 
sis> sis> sis> s420.kiss2.esp	pi=19	po= 2	nodes= 12	latches= 5
lits(sop)=  70	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: s420.kiss2.esp, Power = 359.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s510 --> 
sis> sis> sis> s510.kiss2.esp	pi=19	po= 7	nodes= 43	latches= 6
lits(sop)= 353	#states(STG)=  47
sis> Combinational power estimation, with Zero delay model.
Network: s510.kiss2.esp, Power = 1506.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s820 --> 
sis> sis> sis> s820.kiss2.esp	pi=18	po=19	nodes= 43	latches= 5
lits(sop)= 283	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: s820.kiss2.esp, Power = 1012.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s832 --> 
sis> sis> sis> s832.kiss2.esp	pi=18	po=19	nodes= 43	latches= 5
lits(sop)= 294	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: s832.kiss2.esp, Power = 1059.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- shiftreg --> 
sis> sis> sis> shiftreg.kiss2.esp	pi= 1	po= 1	nodes=  2	latches= 3
lits(sop)=   8	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: shiftreg.kiss2.esp, Power = 115.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sse --> 
sis> sis> sis> sse.kiss2.esp 	pi= 7	po= 7	nodes= 18	latches= 4
lits(sop)= 109	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: sse.kiss2.esp, Power = 505.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- tav --> 
sis> sis> sis> tav.kiss2.esp 	pi= 4	po= 4	nodes=  8	latches= 2
lits(sop)=  27	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: tav.kiss2.esp, Power = 164.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tbk --> 
sis> sis> sis> tbk.kiss2.esp 	pi= 6	po= 3	nodes= 29	latches= 4
lits(sop)= 256	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: tbk.kiss2.esp, Power = 841.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train11 --> 
sis> sis> sis> train11.kiss2.esp	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  17	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: train11.kiss2.esp, Power = 132.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train4 --> 
sis> sis> sis> train4.kiss2.esp	pi= 2	po= 1	nodes=  4	latches= 2
lits(sop)=  14	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: train4.kiss2.esp, Power = 110.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
