sis> UC Berkeley, SIS 1.3.6 (compiled 2007-07-18 12:59:37)
sis> <-- START --> 
sis> sis> <-- bbara --> 
sis> sis> fsmenc_output 	pi= 4	po= 2	nodes=  5	latches= 3
lits(sop)= 106	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 478.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbsse --> 
sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 11	latches= 4
lits(sop)= 307	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1173.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbtas --> 
sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  5	latches= 3
lits(sop)=  50	#states(STG)=   6
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 257.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- beecount --> 
sis> sis> fsmenc_output 	pi= 3	po= 4	nodes=  6	latches= 2
lits(sop)=  96	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 421.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- cse --> 
sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 11	latches= 4
lits(sop)= 671	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1889.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk14 --> 
sis> sis> fsmenc_output 	pi= 3	po= 5	nodes=  8	latches= 3
lits(sop)= 259	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1031.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk15 --> 
sis> sis> fsmenc_output 	pi= 3	po= 5	nodes=  7	latches= 2
lits(sop)= 159	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 642.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk16 --> 
sis> sis> fsmenc_output 	pi= 2	po= 3	nodes=  8	latches= 5
lits(sop)=1058	#states(STG)=  27
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 3425.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk17 --> 
sis> sis> fsmenc_output 	pi= 2	po= 3	nodes=  6	latches= 3
lits(sop)= 114	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 569.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk27 --> 
sis> sis> fsmenc_output 	pi= 1	po= 2	nodes=  5	latches= 3
lits(sop)=  27	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 204.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex1 --> 
sis> sis> fsmenc_output 	pi= 9	po=19	nodes= 24	latches= 5
lits(sop)= 954	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 3128.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex3 --> 
sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  5	latches= 3
lits(sop)=  76	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 396.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex4 --> 
sis> sis> fsmenc_output 	pi= 6	po= 9	nodes= 13	latches= 4
lits(sop)= 276	#states(STG)=  14
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1087.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex5 --> 
sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  4	latches= 2
lits(sop)=  54	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 303.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex6 --> 
sis> sis> fsmenc_output 	pi= 5	po= 8	nodes= 11	latches= 3
lits(sop)= 496	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1569.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex7 --> 
sis> sis> fsmenc_output 	pi= 2	po= 2	nodes=  4	latches= 2
lits(sop)=  54	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 283.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- keyb --> 
sis> sis> fsmenc_output 	pi= 7	po= 2	nodes=  7	latches= 5
lits(sop)=1063	#states(STG)=  19
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 3173.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion9 --> 
sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  24	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 157.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion --> 
sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  24	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 159.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mark1 --> 
sis> sis> fsmenc_output 	pi= 5	po=16	nodes= 20	latches= 4
lits(sop)= 213	#states(STG)=  12
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 888.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mc --> 
sis> sis> fsmenc_output 	pi= 3	po= 5	nodes=  7	latches= 2
lits(sop)=  53	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 246.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- opus --> 
sis> sis> fsmenc_output 	pi= 5	po= 6	nodes= 10	latches= 4
lits(sop)= 305	#states(STG)=   9
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 962.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- planet1 --> 
sis> sis> fsmenc_output 	pi= 7	po=19	nodes= 25	latches= 6
lits(sop)=3338	#states(STG)=  48
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 8402.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- planet --> 
sis> sis> fsmenc_output 	pi= 7	po=19	nodes= 25	latches= 6
lits(sop)=3338	#states(STG)=  48
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 8402.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s1488 --> 
sis> sis> fsmenc_output 	pi= 8	po=19	nodes= 25	latches= 6
lits(sop)=2740	#states(STG)=  48
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 7500.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s1494 --> 
sis> sis> fsmenc_output 	pi= 8	po=19	nodes= 25	latches= 6
lits(sop)=2740	#states(STG)=  48
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 7533.6 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s1 --> 
sis> sis> fsmenc_output 	pi= 8	po= 6	nodes= 11	latches= 5
lits(sop)=1461	#states(STG)=  20
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 4157.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s208 --> 
sis> sis> fsmenc_output 	pi=11	po= 2	nodes=  7	latches= 5
lits(sop)= 108	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 466.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s27 --> 
sis> sis> fsmenc_output 	pi= 4	po= 1	nodes=  4	latches= 3
lits(sop)=  59	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 325.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s298 --> 
sis> sis> fsmenc_output 	pi= 3	po= 6	nodes= 14	latches= 8
lits(sop)=7609	#states(STG)= 135
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 20018.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s386 --> 
sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 11	latches= 4
lits(sop)= 352	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1240.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s420 --> 
sis> sis> fsmenc_output 	pi=19	po= 2	nodes=  7	latches= 5
lits(sop)= 108	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 466.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s510 --> 
sis> sis> fsmenc_output 	pi=19	po= 7	nodes= 13	latches= 6
lits(sop)= 812	#states(STG)=  47
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 2633.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s820 --> 
sis> sis> fsmenc_output 	pi=18	po=19	nodes= 24	latches= 5
lits(sop)=1050	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 3168.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s832 --> 
sis> sis> fsmenc_output 	pi=18	po=19	nodes= 24	latches= 5
lits(sop)=1060	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 3291.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sand --> 
sis> sis> fsmenc_output 	pi=11	po= 9	nodes= 14	latches= 5
lits(sop)=3012	#states(STG)=  32
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 7583.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- shiftreg --> 
sis> sis> fsmenc_output 	pi= 1	po= 1	nodes=  4	latches= 3
lits(sop)=   4	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 95.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sse --> 
sis> sis> fsmenc_output 	pi= 7	po= 7	nodes= 11	latches= 4
lits(sop)= 307	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 1173.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- styr --> 
sis> sis> fsmenc_output 	pi= 9	po=10	nodes= 15	latches= 5
lits(sop)=2465	#states(STG)=  30
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 6383.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tav --> 
sis> sis> fsmenc_output 	pi= 4	po= 4	nodes=  6	latches= 2
lits(sop)=  35	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 200.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tbk --> 
sis> sis> fsmenc_output 	pi= 6	po= 3	nodes=  7	latches= 4
lits(sop)= 852	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 2662.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train11 --> 
sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  14	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 118.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train4 --> 
sis> sis> fsmenc_output 	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  28	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: fsmenc_output, Power = 180.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
