sis> UC Berkeley, SIS 1.3.6 (compiled 2007-07-18 12:59:37)
sis> <-- START --> 
sis> sis> <-- bbara --> 
sis> sis> sis> jedi_output   	pi= 4	po= 2	nodes=  6	latches= 3
lits(sop)=  53	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 305.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbsse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 18	latches= 4
lits(sop)= 121	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 546.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- bbtas --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  7	latches= 3
lits(sop)=  24	#states(STG)=   6
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 172.9 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- beecount --> 
sis> sis> sis> jedi_output   	pi= 3	po= 4	nodes=  6	latches= 2
lits(sop)=  26	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 168.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- cse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 25	latches= 4
lits(sop)= 212	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 764.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk14 --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes= 12	latches= 3
lits(sop)=  96	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 470.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk15 --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes=  9	latches= 2
lits(sop)=  80	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 414.3 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk16 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 3	nodes= 25	latches= 5
lits(sop)= 231	#states(STG)=  27
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1058.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk17 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 3	nodes= 10	latches= 3
lits(sop)=  65	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 361.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- dk27 --> 
sis> sis> sis> jedi_output   	pi= 1	po= 2	nodes=  6	latches= 3
lits(sop)=  22	#states(STG)=   7
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 183.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex1 --> 
sis> sis> sis> jedi_output   	pi= 9	po=19	nodes= 37	latches= 5
lits(sop)= 212	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 884.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex3 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  6	latches= 3
lits(sop)=  27	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 200.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex4 --> 
sis> sis> sis> jedi_output   	pi= 6	po= 9	nodes= 18	latches= 4
lits(sop)=  74	#states(STG)=  14
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 430.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex5 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  3	latches= 2
lits(sop)=  17	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 142.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex6 --> 
sis> sis> sis> jedi_output   	pi= 5	po= 8	nodes= 14	latches= 3
lits(sop)= 105	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 495.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- ex7 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 2	nodes=  4	latches= 2
lits(sop)=  22	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 168.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- keyb --> 
sis> sis> sis> jedi_output   	pi= 7	po= 2	nodes= 23	latches= 5
lits(sop)= 240	#states(STG)=  19
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 996.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion9 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  4	latches= 2
lits(sop)=  15	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 122.8 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- lion --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  14	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 127.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mark1 --> 
sis> sis> sis> jedi_output   	pi= 5	po=16	nodes= 17	latches= 4
lits(sop)=  73	#states(STG)=  12
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 382.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- mc --> 
sis> sis> sis> jedi_output   	pi= 3	po= 5	nodes=  6	latches= 2
lits(sop)=  25	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 173.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- opus --> 
sis> sis> sis> jedi_output   	pi= 5	po= 6	nodes= 14	latches= 4
lits(sop)=  78	#states(STG)=   9
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 414.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s1 --> 
sis> sis> sis> jedi_output   	pi= 8	po= 6	nodes= 13	latches= 5
lits(sop)= 108	#states(STG)=  20
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 516.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s208 --> 
sis> sis> sis> jedi_output   	pi=11	po= 2	nodes= 13	latches= 5
lits(sop)= 111	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 528.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s27 --> 
sis> sis> sis> jedi_output   	pi= 4	po= 1	nodes=  7	latches= 3
lits(sop)=  28	#states(STG)=   5
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 197.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- s386 --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 16	latches= 4
lits(sop)= 119	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 543.4 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s420 --> 
sis> sis> sis> jedi_output   	pi=19	po= 2	nodes= 12	latches= 5
lits(sop)= 119	#states(STG)=  18
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 525.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s510 --> 
sis> sis> sis> jedi_output   	pi=19	po= 7	nodes= 40	latches= 6
lits(sop)= 315	#states(STG)=  47
sis> sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s820 --> 
sis> sis> sis> jedi_output   	pi=18	po=19	nodes= 47	latches= 5
lits(sop)= 325	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1174.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- s832 --> 
sis> sis> sis> jedi_output   	pi=18	po=19	nodes= 49	latches= 5
lits(sop)= 347	#states(STG)=  24
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 1145.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sand --> 
sis> sis> sis> jedi_output   	pi=11	po= 9	nodes= 86	latches= 6
lits(sop)= 655	#states(STG)=  32
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 2314.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- shiftreg --> 
sis> sis> sis> jedi_output   	pi= 1	po= 1	nodes=  4	latches= 3
lits(sop)=  10	#states(STG)=   8
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 117.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- sse --> 
sis> sis> sis> jedi_output   	pi= 7	po= 7	nodes= 18	latches= 4
lits(sop)= 121	#states(STG)=  13
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 546.2 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> sis> sis> sis> sis> sis> sis> sis> sis> <-- START --> 
sis> sis> <-- tav --> 
sis> sis> sis> jedi_output   	pi= 4	po= 4	nodes=  8	latches= 2
lits(sop)=  27	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 164.0 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- tbk --> 
sis> sis> sis> jedi_output   	pi= 6	po= 3	nodes= 28	latches= 4
lits(sop)= 247	#states(STG)=  16
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 841.7 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train11 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  3	latches= 2
lits(sop)=  11	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 108.1 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
sis> <-- START --> 
sis> sis> <-- train4 --> 
sis> sis> sis> jedi_output   	pi= 2	po= 1	nodes=  4	latches= 2
lits(sop)=  17	#states(STG)=   4
sis> Combinational power estimation, with Zero delay model.
Network: jedi_output, Power = 116.5 uW assuming 20 MHz clock and Vdd = 5V
sis> <-- END --> 
