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<h1>Actual Projects</h1>
Please replace ?at? with @ in email address
<ul class="projects">
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/BOOM">BOOM-II - A Boolean Minimizer</a>
  		<ul class="sez">
  			<li class="liche">A heuristic two-level minimizer for Boolean functions with many inputs and outputs</li>
  			<li class="sude">Contact person: <a href="mailto:fiserp?at?fel.cvut.cz">Petr Fišer</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/BoomBench">BOOM Benchmarks</a>
  		<ul class="sez">
  			<li class="liche">Set of artificial standard benchmarks</li>
  			<li class="sude">Two-level logic circuits - PLAs</li>
  			<li class="liche">Contact person: <a href="mailto:fiserp?at?fel.cvut.cz">Petr Fišer</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/PLA_gen">PLA Generator</a>
  		<ul class="sez">
  			<li class="liche">Parametrized generator of random Boolean functions, in the PLA format</li>
  			<li class="sude">Contact person: <a href="mailto:fiserp?at?fel.cvut.cz">Petr Fišer</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/ColMatch">ColMatch - A BIST design tool</a>
  		<ul class="sez">
  			<li class="liche">Test-per-clock mixed-mode BIST</li>
  			<li class="sude">Contact person: <a href="mailto:fiserp?at?fel.cvut.cz">Petr Fišer</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/DZU">DZU benchmark database</a>
  		<ul class="sez">
  			<li class="liche">Database of standard logis synthesis benchmarks</li>
  			<li class="sude">Contact person: <a href="mailto:kubatova?at?fel.cvut.cz">Hana Kubátová</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://cs.felk.cvut.cz/~danek/research/mapper/adaptmap-index.html">ADAPTMAP - an adaptive mapper for LUT-based FPGAs</a>
  		<ul class="sez">
  			<li class="liche">General-purpose mapping algorithm that will be able to adapt its behaviour according to user-supplied properties of a target FPGA device</li>
  			<li class="sude">Contact person: <a href="mailto:danek?at?fel.cvut.cz">Martin Daněk</a></li>
  		</ul><br /></li>

  <li> <a target="_blank" href="http://cs.felk.cvut.cz/~danek/research/place">Timing-driven physical design algorithms</a>
  		<ul class="sez">
  			<li class="liche">Implementing and testing a placement / global routing algorithm based on an integrated approach</li>
  			<li class="sude">Contact person: <a href="mailto:danek?at?fel.cvut.cz">Martin Daněk</a></li>
  		</ul><br /></li>
  		
  <li><a target="_blank" href="http://www.utia.cas.cz/ZS/home.php?ids=ga2137">Dynamically reconfigurable FPGAs</a>
  		<ul class="sez">
  			<li class="liche">FPGA design methodology</li>
  			<li class="sude">Fault tolerant, fail safe and space effective design</li>
  			<li class="liche">Practical implementation in ATMEL products</li>
  			<li class="sude">Contact person: <a href="mailto:danek?at?fel.cvut.cz">Martin Daněk</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/PetriNets/">Petri nets</a>
  		<ul class="sez">
  			<li class="liche">Direct implementation of PN in FPGA</li>
  			<li class="sude">Practical models in Design/CPN and other professional Petri Nets design tools</li>
  			<li class="liche">Contact person: <a href="mailto:kubatova?at?fel.cvut.cz">Hana Kubátová</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/FSM/">Optimal FSM implementation in FPGAs</a>
  		<ul class="sez">
  			<li class="liche">Searching for the properties, parameters and way of finite state machine (FSM) description</li>
  			<li class="sude">Coding and decomposition of FSMs</li>
  			<li class="liche">Optimal implementation of combinational circuits</li>
  			<li class="sude">Contact person: <a href="mailto:kubatova?at?fel.cvut.cz">Hana Kubátová</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/ECDSA/">Arithmetic Hardware for <i>GF</i>(2<i><sup>m</sup></i>)</a>
  		<ul class="sez">
  			<li class="liche">Development of arithmetic units that can be scaled according to the given purpose and environment</li>
  			<li class="sude">Interaction between algorithms and FPGA architecture</li>
  			<li class="liche">Application fields – embedded cryptographic systems</li>
  			<li class="sude">Contact person: <a href="mailto:schmidt?at?fel.cvut.cz">Jan Schmidt</a></li>
  		</ul><br /></li>
  		
  <li>Processor architectures
  		<ul class="sez">
  			<li class="liche">Processor for educational purposes – DOP</li>
  			<li class="sude">Hardware support for garbage collection</li>
  			<li class="liche">Reconfigurable microprogrammed controllers</li>
  			<li class="sude">Contact person: <a href="mailto:becvarm?at?fel.cvut.cz">Miloš Bečvář</a></li>
  		</ul><br /></li>
  		
  <li>Complex EDA system for educational purposes
  		<ul class="sez">
  			<li class="liche">Experimental Electronic Design Automation software</li>
  			<li class="sude">For testing new algorithms</li>
  			<li class="liche">For simple use</li>
  			<li class="sude">Contact person: <a href="mailto:fiserp?at?fel.cvut.cz">Petr Fišer</a>, <a href="mailto:schmidt?at?fel.cvut.cz">Jan Schmidt</a></li>
  		</ul><br /></li>
  		
  <li> <a target="_blank" href="http://service.felk.cvut.cz/vlsi/prj/Atalanta-M/">Atalanta-M</a>
  		<ul class="sez">
  			<li class="liche">Modified ATALANTA z VirginiaTech</li>
  			<li class="sude">ATPG and fault simulator joined into one tool</li>
  			<li class="liche">Extended interface</li>
  			<li class="sude">Contact person: <a href="mailto:fiserp?at?fel.cvut.cz">Petr Fišer</a></li>
  		</ul><br /></li>
</ul>




<br />
<hr />
<br />
<h1>Past Major Projects</h1>
<ul class="sez">
	<li class="liche"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g10440.html">Formal Procedures in Diagnostics of Digital Circuits - Verification of Testable Design</a> (GA 102/01/1531, 2001-2003)</li>
	<li class="sude"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g10441.html">Built-in Self-test Equipment Optimisation Methods in Integrated Circuits</a> (GA 102/01/0566, 2001-2003)</li>
	<li class="liche"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g9872.html">Fault Injection for TTA</a> (OKIX IST-1999-10748, 2000-2002)</li>
	<li class="sude"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g9273.html">Research into Methods for Speeding up Computations Using Reconfigurable Hardware</a> (GA 102/99/1017, 1999-2001)</li>
	<li class="liche"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g8907.html">Methods and Tools for Testability Analysis of Digital Circuits</a> (GA 102/98/1463, 1998-2000)</li>
	<li class="sude"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g8906.html">Research and Application of at Built-In Self-Test for IC</a> (GA 102/98/1003, 1998-2000)</li>
	<li class="liche"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g8176.html">COPRODES - A CAD System for Automatic Design of FPGA-Based Communication Processors</a> (<a target="_blank" href="http://www.cordis.lu/esprit/src/intclink.htm">EU Copernicus</a>, 1995-1998)</li>
	</ul>
	
<h1>Funding</h1>
<h2>Grants</h2>
<ul class="sez">
	<li class="liche"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g16423.html">Innovation of Laboratory for Education of SoC Digital Design</a> (FRVS, 2005)</li>
	<li class="sude"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g17296.html">Use of speculative computation for arithmetic accelerating</a> (CTU, 2005)</li>
	<li class="liche"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g15261.html">Modern Methods of Digital System Synthesis</a> (GA102/04/0737, 2004-2006)</li>
	<li class="sude"><a target="_blank" href="http://cs.felk.cvut.cz/webis/en/research_/g15262.html">Design of Highly Reliable Control Systems Built on Dynamically Reconfigurable FPGAs</a> (GA102/04/2137, 2004-2006)</li>

</ul>

<h1>Cooperating Institutions</h1>
<ul class="sez">
  <li class="liche"><a target="_blank" href="http://www.utia.cas.cz">UTIA</a> at the <a target="_blank" href="http://www.cas.cz">Czech Academy of Science</a></li>
  <li class="sude"><a target="_blank" href="http://www.s3group.cz">Silicon and Software Systems CR</a></li>
  <li class="liche"><a target="_blank" href="http://www.csm.uwe.ac.uk/icsc">ICSC</a> at the <a target="_blank" href="http://www.uwe.ac.uk">University of the West of England</a> </li>
  <li class="sude"><a target="_blank" href="http://www.asicentrum.cz">ASICentrum</a> </li>
  <li class="liche"><a target="_blank" href="http://www.fit.vutbr.cz/units/UPSY">UPSY</a> , <a target="_blank" href="http://www.fit.vutbr.cz">Faculty of Information Technology</a> at <a target="_blank" href="http://www.vutbr.cz">Brno University of Technology</a> </li>
  <li class="sude"><a target="_blank" href="http://www.fm.vslib.cz/htm/naviga_eng.htm">Faculty of Mechatronics</a> at the <a target="_blank" href="http://www.vslib.cz">Technical University of Liberec</a></li>
  <li class="liche"><a target="_blank" href="http://www.zcu.cz/index-en.html">University of West Bohemia</a> </li>
</ul>
	
	
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