\chapter{Export do VHDL}

\section{Struktura uložená v HUBu}
\label{export_vstup}
\begin{verbatim}
+unit
    +library bench_primitives
	+entity and3
	    =port I1 attr in 
	    =port I2 attr in 
	    =port I3 attr in 
	    =port O attr out 
	    +arch bench attr behav 
		symmetric func AND, 3 inputs
	    -arch bench
	-entity and3
	+entity dff1
	    =port D attr in 
	    =port O attr out 
	    =port Q attr out 
	    +arch bench attr behav 
		RTL register
	    -arch bench
	-entity dff1
	+entity nand2
	    =port I1 attr in 
	    =port I2 attr in 
	    =port O attr out 
	    +arch bench attr behav 
		symmetric func NAND, 2 inputs
	    -arch bench
	-entity nand2
	+entity nor2
	    =port I1 attr in 
	    =port I2 attr in 
	    =port O attr out 
	    +arch bench attr behav 
		symmetric func NOR, 2 inputs
	    -arch bench
	-entity nor2
	+entity not1
	    =port I1 attr in 
	    =port O attr out 
	    +arch bench attr behav 
		symmetric func INV, 1 inputs
	    -arch bench
	-entity not1
	+entity or2
	    =port I1 attr in 
	    =port I2 attr in 
	    =port O attr out 
	    +arch bench attr behav 
		symmetric func OR, 2 inputs
	    -arch bench
	-entity or2
	+entity or3
	    =port I1 attr in 
	    =port I2 attr in 
	    =port I3 attr in 
	    =port O attr out 
	    +arch bench attr behav 
		symmetric func OR, 3 inputs
	    -arch bench
	-entity or3
    -library bench_primitives
    +library work
	+entity s27
	    =port G0 attr in 
	    =port G1 attr in 
	    =port G17 attr out 
	    =port G2 attr in 
	    =port G3 attr in 
	    +arch bench attr struct 
		=instance G10 nor2.bench_primitives
		=instance G11 nor2.bench_primitives
		=instance G12 nor2.bench_primitives
		=instance G13 nor2.bench_primitives
		=instance G14 not1.bench_primitives
		=instance G15 or3.bench_primitives
		=instance G16 or2.bench_primitives
		=instance G17 not1.bench_primitives
		=instance G5 dff1.bench_primitives
		=instance G6 dff1.bench_primitives
		=instance G7 dff1.bench_primitives
		=instance G8 and3.bench_primitives
		=instance G9 nand2.bench_primitives
		+net G0 G0, I1.G14, I3.G15
		-net G0
		+net G1 G1, I1.G12
		-net G1
		+net G10 D.G5, O.G10
		-net G10
		+net G11 D.G6, I1.G17, I2.G10, O.G11
		-net G11
		+net G12 I1.G15, O.G12, I2.G13
		-net G12
		+net G13 D.G7, O.G13
		-net G13
		+net G14 O.G14, I1.G8, I1.G10
		-net G14
		+net G15 O.G15, I2.G9
		-net G15
		+net G16 O.G16, I1.G9
		-net G16
		+net G17 G17, O.G17
		-net G17
		+net G2 G2, I1.G13
		-net G2
		+net G3 G3, I1.G16
		-net G3
		+net G5 O.G5, I1.G11
		-net G5
		+net G6 O.G6, I2.G8
		-net G6
		+net G7 O.G7, I3.G8, I2.G12
		-net G7
		+net G8 O.G8, I2.G15, I2.G16
		-net G8
		+net G9 O.G9, I2.G11
		-net G9
	    -arch bench
	-entity s27
    -library work
-unit
\end{verbatim}

\section{Výstup ve formátu VHDL}
\label{export_vystup}
\subsection{Knihovna work}
\begin{verbatim}
library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity s27 is
  port (
    G0 : in std_logic;
    G1 : in std_logic;
    G17 : out std_logic;
    G2 : in std_logic;
    G3 : in std_logic
  );
end entity s27;

architecture bench of s27 is
  signal G10 : std_logic;
  signal G11 : std_logic;
  signal G12 : std_logic;
  signal G13 : std_logic;
  signal G14 : std_logic;
  signal G15 : std_logic;
  signal G16 : std_logic;
  signal G5 : std_logic;
  signal G6 : std_logic;
  signal G7 : std_logic;
  signal G8 : std_logic;
  signal G9 : std_logic;
  
  component dff1
    port (
      D : in std_logic;
      O : out std_logic;
      Q : out std_logic
    );
  end component;
  
begin

  G10 <= G14 nor G11;
  G11 <= G5 nor G9;
  G12 <= G1 nor G7;
  G13 <= G2 nor G12;
  G14 <= not G0;
  G15 <= G12 or G8 or G0;
  G16 <= G3 or G8;
  G17 <= not G11;
  G5: dff1
   port map(
     O => G5,
     D => G10,
     Q => open
   );
  G6: dff1
   port map(
     O => G6,
     D => G11,
     Q => open
   );
  G7: dff1
   port map(
     O => G7,
     D => G13,
     Q => open
   );
  G8 <= G14 and G6 and G7;
  G9 <= G16 nand G15;
end architecture bench;

\end{verbatim}
\subsection{Knihovna bench\_primitives}
\begin{verbatim}
library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity and3 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    I3 : in std_logic;
    O : out std_logic
  );
end entity and3;

architecture bench of and3 is
begin
  O <= I1 and I2 and I3;
end architecture bench;

entity dff1 is
  port (
    D : in std_logic;
    O : out std_logic;
    Q : out std_logic
  );
end entity dff1;

architecture bench of dff1 is
begin
  -- unknown architecture
end architecture bench;

entity nand2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity nand2;

architecture bench of nand2 is
begin
  O <= I1 nand I2;
end architecture bench;

entity nor2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity nor2;

architecture bench of nor2 is
begin
  O <= I1 nor I2;
end architecture bench;

entity not1 is
  port (
    I1 : in std_logic;
    O : out std_logic
  );
end entity not1;

architecture bench of not1 is
begin
  O <= not I1;
end architecture bench;

entity or2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity or2;

architecture bench of or2 is
begin
  O <= I1 or I2;
end architecture bench;

entity or3 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    I3 : in std_logic;
    O : out std_logic
  );
end entity or3;

architecture bench of or3 is
begin
  O <= I1 or I2 or I3;
end architecture bench;

\end{verbatim}
