library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity s27 is
  port (
    G0 : in std_logic;
    G1 : in std_logic;
    G17 : out std_logic;
    G2 : in std_logic;
    G3 : in std_logic
  );
end entity s27;

architecture bench of s27 is
  signal G10 : std_logic;
  signal G11 : std_logic;
  signal G12 : std_logic;
  signal G13 : std_logic;
  signal G14 : std_logic;
  signal G15 : std_logic;
  signal G16 : std_logic;
  signal G5 : std_logic;
  signal G6 : std_logic;
  signal G7 : std_logic;
  signal G8 : std_logic;
  signal G9 : std_logic;
  
  component dff1
    port (
      D : in std_logic;
      O : out std_logic;
      Q : out std_logic
    );
  end component;
  
begin

  G10 <= G14 nor G11;
  G11 <= G5 nor G9;
  G12 <= G1 nor G7;
  G13 <= G2 nor G12;
  G14 <= not G0;
  G15 <= G12 or G8 or G0;
  G16 <= G3 or G8;
  G17 <= not G11;
  G5: dff1
   port map(
     O => G5,
     D => G10,
     Q => open
   );
  G6: dff1
   port map(
     O => G6,
     D => G11,
     Q => open
   );
  G7: dff1
   port map(
     O => G7,
     D => G13,
     Q => open
   );
  G8 <= G14 and G6 and G7;
  G9 <= G16 nand G15;
end architecture bench;
