\chapter{Import VHDL}

\section{Vstupní soubor}

\subsection{Poloviční sčítačka - halfadder.vhdl}
\label{import_vstup}
\begin{verbatim}
library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity halfadder is
  port ( 
     A: in std_logic;
     B: in std_logic;
     S: out std_logic;
     Carry: out std_logic     
    );
end halfadder;

ARCHITECTURE halfadder_arch OF halfadder IS

BEGIN
	S <= A xor B;
	Carry <= A and B;

END halfadder_arch;
\end{verbatim}

\subsection{1-bitová úplná sčítačka - adder.vhdl}
\begin{verbatim}
library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity adder is
  port ( 
     A: in std_logic;
     B: in std_logic;
     C: in std_logic;
     SUM: out std_logic;
     Carry: out std_logic     
    );
end adder;

ARCHITECTURE adder_arch OF adder IS

signal c1, c2, s: std_logic;

component halfadder
  port ( 
     A: in std_logic;
     B: in std_logic;
     S: out std_logic;
     Carry: out std_logic     
    );
end component;

BEGIN
	H1_map: halfadder
		port map(A => A,
				B => B,
				Carry => c1,
				S => s);
	H2_map: halfadder
		port map(A => C,
				B => s,
				Carry => c2,
				S => SUM);
	
	Carry <= c1 or c2;

END adder_arch;
\end{verbatim}

\subsection{4-bitová sčítačka - 4bitAdder.vhdl}
\begin{verbatim}
library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity FourBitAdder is
  port ( 
     IN_1: in std_logic_vector(3 downto 0);
     IN_2: in std_logic_vector(3 downto 0);
     SUM: out std_logic_vector(3 downto 0);
     Carry: out std_logic     
    );
end FourBitAdder;

ARCHITECTURE FourBitAdder_arch OF FourBitAdder IS

signal c: std_logic_vector(2 downto 0);

component halfadder
  port ( 
     A: in std_logic;
     B: in std_logic;
     S: out std_logic;
     Carry: out std_logic     
    );
end component;

component adder
  port ( 
     A: in std_logic;
     B: in std_logic;
     C: in std_logic;
     SUM: out std_logic;
     Carry: out std_logic     
    );
end component;

BEGIN
	H_map: halfadder
		port map(A => IN_1(0),
				B => IN_2(0),
				Carry => c(0),
				S => SUM(0));
	A1_map: adder
		port map(A => IN_1(1),
				B => IN_2(1),
				C => c(0),
				Carry => c(1),
				SUM => SUM(1));
	A2_map: adder
		port map(A => IN_1(2),
				B => IN_2(2),
				C => c(1),
				Carry => c(2),
				SUM => SUM(2));
	A3_map: adder
		port map(A => IN_1(3),
				B => IN_2(3),
				C => c(2),
				Carry => Carry,
				SUM => SUM(3));

END FourBitAdder_arch;
\end{verbatim}

\section{Výstupní soubor}
\subsection{Dbg výstup}
\label{import_vystup}
\begin{verbatim}
+unit
    +library primitives
	+entity and2
	    =port I1 attr in 
	    =port I2 attr in 
	    =port O attr out 
	    +arch vhdl attr behav 
		symmetric func AND, 2 inputs
	    -arch vhdl
	-entity and2
	+entity or2
	    =port I1 attr in 
	    =port I2 attr in 
	    =port O attr out 
	    +arch vhdl attr behav 
		symmetric func OR, 2 inputs
	    -arch vhdl
	-entity or2
	+entity xor2
	    =port I1 attr in 
	    =port I2 attr in 
	    =port O attr out 
	    +arch vhdl attr behav 
		symmetric func XOR, 2 inputs
	    -arch vhdl
	-entity xor2
    -library primitives
    +library work
	+entity adder
	    =port A attr in 
	    =port B attr in 
	    =port C attr in 
	    =port Carry attr out 
	    =port SUM attr out 
	    +arch adder_arch attr struct 
		=instance H1_map halfadder
		=instance H2_map halfadder
		=instance or2_1 or2.primitives
		+net A A, A.H1_map
		-net A
		+net B B, B.H1_map
		-net B
		+net C C, A.H2_map
		-net C
		+net c1 Carry.H1_map, I1.or2_1
		-net c1
		+net c2 Carry.H2_map, I2.or2_1
		-net c2
		+net Carry Carry, O.or2_1
		-net Carry
		+net s S.H1_map, B.H2_map
		-net s
		+net SUM SUM, S.H2_map
		-net SUM
	    -arch adder_arch
	-entity adder
	+entity FourBitAdder
	    =port Carry attr out 
	    =port IN_1_0 attr in 
	    =port IN_1_1 attr in 
	    =port IN_1_2 attr in 
	    =port IN_1_3 attr in 
	    =port IN_2_0 attr in 
	    =port IN_2_1 attr in 
	    =port IN_2_2 attr in 
	    =port IN_2_3 attr in 
	    =port SUM_0 attr out 
	    =port SUM_1 attr out 
	    =port SUM_2 attr out 
	    =port SUM_3 attr out 
	    +arch FourBitAdder_arch attr struct 
		=instance A1_map adder
		=instance A2_map adder
		=instance A3_map adder
		=instance H_map halfadder
		+net c_0 Carry.H_map, C.A1_map
		-net c_0
		+net c_1 Carry.A1_map, C.A2_map
		-net c_1
		+net c_2 Carry.A2_map, C.A3_map
		-net c_2
		+net Carry Carry, Carry.A3_map
		-net Carry
		+net IN_1_0 IN_1_0, A.H_map
		-net IN_1_0
		+net IN_1_1 IN_1_1, A.A1_map
		-net IN_1_1
		+net IN_1_2 IN_1_2, A.A2_map
		-net IN_1_2
		+net IN_1_3 IN_1_3, A.A3_map
		-net IN_1_3
		+net IN_2_0 IN_2_0, B.H_map
		-net IN_2_0
		+net IN_2_1 IN_2_1, B.A1_map
		-net IN_2_1
		+net IN_2_2 IN_2_2, B.A2_map
		-net IN_2_2
		+net IN_2_3 IN_2_3, B.A3_map
		-net IN_2_3
		+net SUM_0 SUM_0, S.H_map
		-net SUM_0
		+net SUM_1 SUM_1, SUM.A1_map
		-net SUM_1
		+net SUM_2 SUM_2, SUM.A2_map
		-net SUM_2
		+net SUM_3 SUM_3, SUM.A3_map
		-net SUM_3
	    -arch FourBitAdder_arch
	-entity FourBitAdder
	+entity halfadder
	    =port A attr in 
	    =port B attr in 
	    =port Carry attr out 
	    =port S attr out 
	    +arch halfadder_arch attr struct 
		=instance and2_1 and2.primitives
		=instance xor2_1 xor2.primitives
		+net A A, I1.xor2_1, I1.and2_1
		-net A
		+net B B, I2.xor2_1, I2.and2_1
		-net B
		+net Carry Carry, O.and2_1
		-net Carry
		+net S S, O.xor2_1
		-net S
	    -arch halfadder_arch
	-entity halfadder
    -library work
-unit
\end{verbatim}
