library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity c17 is
  port (
    G1gat : in std_logic;
    G22gat : out std_logic;
    G23gat : out std_logic;
    G2gat : in std_logic;
    G3gat : in std_logic;
    G6gat : in std_logic;
    G7gat : in std_logic
  );
end entity c17;

architecture arch of c17 is
  
  component LUT4
    port (
      I0 : in std_logic;
      I1 : in std_logic;
      I2 : in std_logic;
      I3 : in std_logic;
      O : out std_logic
    );
  end component;
  
begin

  g22gat_i: LUT4
   port map(
     I0 => g2gat,
     I1 => g3gat,
     I2 => g1gat,
     I3 => g6gat,
     O => g22gat
   );
  g23gat_i: LUT4
   port map(
     I0 => g7gat,
     I1 => g2gat,
     I2 => g6gat,
     I3 => g3gat,
     O => g23gat
   );
end architecture arch;
