library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity halfadder is
  port ( 
     A: in std_logic;
     B: in std_logic;
     S: out std_logic;
     Carry: out std_logic     
    );
end halfadder;

ARCHITECTURE halfadder_arch OF halfadder IS

BEGIN
	S <= A xor B;
	Carry <= A and B;

END halfadder_arch;
