library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity adder is
  port ( 
     A: in std_logic;
     B: in std_logic;
     C: in std_logic;
     SUM: out std_logic;
     Carry: out std_logic     
    );
end adder;

ARCHITECTURE adder_arch OF adder IS

signal c1, c2, s: std_logic;

component halfadder
  port ( 
     A: in std_logic;
     B: in std_logic;
     S: out std_logic;
     Carry: out std_logic     
    );
end component;

BEGIN
	H1_map: halfadder
		port map(A => A,
				B => B,
				Carry => c1,
				S => s);
	H2_map: halfadder
		port map(A => C,
				B => s,
				Carry => c2,
				S => SUM);
	
	Carry <= c1 or c2;

END adder_arch;
