library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity nand2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity nand2;

architecture bench of nand2 is
begin
  O <= I1 nand I2;
end architecture bench;
