library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity FourBitAdder is
  port ( 
     IN_1: in std_logic_vector(3 downto 0);
     IN_2: in std_logic_vector(3 downto 0);
     SUM: out std_logic_vector(3 downto 0);
     Carry: out std_logic     
    );
end FourBitAdder;

ARCHITECTURE FourBitAdder_arch OF FourBitAdder IS

signal c: std_logic_vector(2 downto 0);

component halfadder
  port ( 
     A: in std_logic;
     B: in std_logic;
     S: out std_logic;
     Carry: out std_logic     
    );
end component;

component adder
  port ( 
     A: in std_logic;
     B: in std_logic;
     C: in std_logic;
     SUM: out std_logic;
     Carry: out std_logic     
    );
end component;

BEGIN
	H_map: halfadder
		port map(A => IN_1(0),
				B => IN_2(0),
				Carry => c(0),
				S => SUM(0));
	A1_map: adder
		port map(A => IN_1(1),
				B => IN_2(1),
				C => c(0),
				Carry => c(1),
				SUM => SUM(1));
	A2_map: adder
		port map(A => IN_1(2),
				B => IN_2(2),
				C => c(1),
				Carry => c(2),
				SUM => SUM(2));
	A3_map: adder
		port map(A => IN_1(3),
				B => IN_2(3),
				C => c(2),
				Carry => Carry,
				SUM => SUM(3));

END FourBitAdder_arch;
