library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity and3 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    I3 : in std_logic;
    O : out std_logic
  );
end entity and3;

architecture bench of and3 is
begin
  O <= I1 and I2 and I3;
end architecture bench;

entity dff1 is
  port (
    D : in std_logic;
    O : out std_logic;
    Q : out std_logic
  );
end entity dff1;

architecture bench of dff1 is
begin
  -- unknown architecture
end architecture bench;

entity nand2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity nand2;

architecture bench of nand2 is
begin
  O <= I1 nand I2;
end architecture bench;

entity nor2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity nor2;

architecture bench of nor2 is
begin
  O <= I1 nor I2;
end architecture bench;

entity not1 is
  port (
    I1 : in std_logic;
    O : out std_logic
  );
end entity not1;

architecture bench of not1 is
begin
  O <= not I1;
end architecture bench;

entity or2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity or2;

architecture bench of or2 is
begin
  O <= I1 or I2;
end architecture bench;

entity or3 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    I3 : in std_logic;
    O : out std_logic
  );
end entity or3;

architecture bench of or3 is
begin
  O <= I1 or I2 or I3;
end architecture bench;
