library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity LUT4 is
  port (
    I0 : in std_logic;
    I1 : in std_logic;
    I2 : in std_logic;
    I3 : in std_logic;
    O : out std_logic
  );
end entity LUT4;

architecture PRIM of LUT4 is
begin

end architecture PRIM;
