library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity and2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity and2;

architecture vhdl of and2 is
begin
  O <= I1 and I2;
end architecture vhdl;

entity or2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity or2;

architecture vhdl of or2 is
begin
  O <= I1 or I2;
end architecture vhdl;

entity xor2 is
  port (
    I1 : in std_logic;
    I2 : in std_logic;
    O : out std_logic
  );
end entity xor2;

architecture vhdl of xor2 is
begin
  O <= I1 xor I2;
end architecture vhdl;
