library IEEE;
use ieee.Std_Logic_1164.all;
use ieee.numeric_std.all;

entity adder is
  port (
    A : in std_logic;
    B : in std_logic;
    C : in std_logic;
    Carry : out std_logic;
    SUM : out std_logic
  );
end entity adder;

architecture adder_arch of adder is
  signal c1 : std_logic;
  signal c2 : std_logic;
  signal s : std_logic;
  
  component halfadder
    port (
      A : in std_logic;
      B : in std_logic;
      Carry : out std_logic;
      S : out std_logic
    );
  end component;
  
begin

  H1_map: halfadder
   port map(
     A => A,
     B => B,
     S => s,
     Carry => c1
   );
  H2_map: halfadder
   port map(
     A => C,
     B => s,
     S => SUM,
     Carry => c2
   );
  Carry <= c1 or c2;
end architecture adder_arch;

entity FourBitAdder is
  port (
    Carry : out std_logic;
    IN_1_0 : in std_logic;
    IN_1_1 : in std_logic;
    IN_1_2 : in std_logic;
    IN_1_3 : in std_logic;
    IN_2_0 : in std_logic;
    IN_2_1 : in std_logic;
    IN_2_2 : in std_logic;
    IN_2_3 : in std_logic;
    SUM_0 : out std_logic;
    SUM_1 : out std_logic;
    SUM_2 : out std_logic;
    SUM_3 : out std_logic
  );
end entity FourBitAdder;

architecture FourBitAdder_arch of FourBitAdder is
  signal c_0 : std_logic;
  signal c_1 : std_logic;
  signal c_2 : std_logic;
  
  component adder
    port (
      A : in std_logic;
      B : in std_logic;
      C : in std_logic;
      Carry : out std_logic;
      SUM : out std_logic
    );
  end component;
  
  component halfadder
    port (
      A : in std_logic;
      B : in std_logic;
      Carry : out std_logic;
      S : out std_logic
    );
  end component;
  
begin

  A1_map: adder
   port map(
     A => IN_1_1,
     B => IN_2_1,
     C => c_0,
     SUM => SUM_1,
     Carry => c_1
   );
  A2_map: adder
   port map(
     A => IN_1_2,
     B => IN_2_2,
     C => c_1,
     SUM => SUM_2,
     Carry => c_2
   );
  A3_map: adder
   port map(
     A => IN_1_3,
     B => IN_2_3,
     C => c_2,
     SUM => SUM_3,
     Carry => Carry
   );
  H_map: halfadder
   port map(
     A => IN_1_0,
     B => IN_2_0,
     S => SUM_0,
     Carry => c_0
   );
end architecture FourBitAdder_arch;

entity halfadder is
  port (
    A : in std_logic;
    B : in std_logic;
    Carry : out std_logic;
    S : out std_logic
  );
end entity halfadder;

architecture halfadder_arch of halfadder is
begin

  Carry <= A and B;
  S <= A xor B;
end architecture halfadder_arch;
